Date: Wed, 14 Dec 2005 04:03:23 GMT From: Warner Losh <imp@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 88170 for review Message-ID: <200512140403.jBE43NlK012099@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=88170 Change 88170 by imp@imp_plunger on 2005/12/14 04:02:23 Extract out of today's work the cpu_reset implementation. Affected files ... .. //depot/projects/arm/src/sys/arm/at91/at91rm92.c#5 edit .. //depot/projects/arm/src/sys/arm/at91/at91rm92reg.h#6 edit Differences ... ==== //depot/projects/arm/src/sys/arm/at91/at91rm92.c#5 (text+ko) ==== @@ -233,7 +233,17 @@ void cpu_reset(void) { - while (1); + struct at91rm92_softc *sc = at91rm92_softc; + + /* + * Reset the CPU by programmig the watchdog timer to reset the + * CPU after 128 'slow' clocks, or about ~4ms. Loop until + * the reset happens for safety. + */ + bus_space_write_4(sc->sc_st, sc->sc_sys_sh, ST_WDMR, ST_RSTEN | 2); + bus_space_write_4(sc->sc_st, sc->sc_sys_sh, ST_CR, ST_WDRST); + while (1) + continue; } static struct resource * ==== //depot/projects/arm/src/sys/arm/at91/at91rm92reg.h#6 (text+ko) ==== @@ -280,6 +280,19 @@ #define PIOD_OWDR (0xa00 + 164) /* Output write disable register */ #define PIOD_OWSR (0xa00 + 168) /* Output write status register */ +#define ST_CR (0xd00 + 0) /* Control register */ +#define ST_WDRST 1 +#define ST_PIMR (0xd00 + 4) /* Period Interval Mode register */ +#define ST_WDMR (0xd00 + 8) /* Watchdog Mode register */ +#define ST_RSTEN (1 << 16) +#define ST_RTMR (0xd00 + 12) /* Reat-time Mode register */ +#define ST_SR (0xd00 + 16) /* Status register */ +#define ST_IER (0xd00 + 20) /* Interrupt Enable register */ +#define ST_IDR (0xd00 + 24) /* Interrupt Disable register */ +#define ST_IMR (0xd00 + 28) /* Interrupt Mask register */ +#define ST_RTAR (0xd00 + 32) /* Real-time Alarm register */ +#define ST_CRTR (0xd00 + 36) /* Current Real-time register */ + /* IRQs : */ /* * 0: AIC
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