Date: Sat, 14 Jul 2018 14:20:31 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-11@freebsd.org Subject: svn commit: r336278 - in stable/11: . contrib/compiler-rt/lib/sanitizer_common contrib/libc++/include contrib/libc++/src/support/runtime contrib/llvm/include/llvm/CodeGen contrib/llvm/include/llvm/... Message-ID: <201807141420.w6EEKV9v055500@repo.freebsd.org>
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Author: dim Date: Sat Jul 14 14:20:30 2018 New Revision: 336278 URL: https://svnweb.freebsd.org/changeset/base/336278 Log: MFC r335799: Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ to 6.0.1 release (upstream r335540). Relnotes: yes MFC r335813: Follow-up to r335799 (llvm/clang 6.0.1 update), by regenerating various headers with new version information defines. MFC r335819: More follow-up to r335799 (llvm/clang 6.0.1 update), where I forgot to update mtree files, ObsoleteFiles and a number of other paths. Sorry about all the breakage. Pointy hat to: me Modified: stable/11/ObsoleteFiles.inc stable/11/UPDATING stable/11/contrib/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cc stable/11/contrib/libc++/include/list stable/11/contrib/libc++/src/support/runtime/exception_libcxxabi.ipp stable/11/contrib/llvm/include/llvm/CodeGen/TargetInstrInfo.h stable/11/contrib/llvm/include/llvm/IR/IntrinsicsPowerPC.td stable/11/contrib/llvm/lib/Analysis/GlobalsModRef.cpp stable/11/contrib/llvm/lib/Analysis/MemorySSA.cpp stable/11/contrib/llvm/lib/CodeGen/IfConversion.cpp stable/11/contrib/llvm/lib/CodeGen/LiveDebugVariables.cpp stable/11/contrib/llvm/lib/CodeGen/MachineBlockPlacement.cpp stable/11/contrib/llvm/lib/CodeGen/PeepholeOptimizer.cpp stable/11/contrib/llvm/lib/CodeGen/TargetInstrInfo.cpp stable/11/contrib/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp stable/11/contrib/llvm/lib/IR/Core.cpp stable/11/contrib/llvm/lib/MC/MCObjectFileInfo.cpp stable/11/contrib/llvm/lib/Support/Host.cpp stable/11/contrib/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp stable/11/contrib/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp stable/11/contrib/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp stable/11/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp stable/11/contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.td stable/11/contrib/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp stable/11/contrib/llvm/lib/Target/AMDGPU/SIISelLowering.cpp stable/11/contrib/llvm/lib/Target/AMDGPU/SIInstructions.td stable/11/contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp stable/11/contrib/llvm/lib/Target/ARM/ARMComputeBlockSize.cpp stable/11/contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp stable/11/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp stable/11/contrib/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td stable/11/contrib/llvm/lib/Target/Mips/MicroMipsInstrInfo.td stable/11/contrib/llvm/lib/Target/Mips/Mips.td stable/11/contrib/llvm/lib/Target/Mips/Mips32r6InstrInfo.td stable/11/contrib/llvm/lib/Target/Mips/Mips64InstrInfo.td stable/11/contrib/llvm/lib/Target/Mips/Mips64r6InstrInfo.td stable/11/contrib/llvm/lib/Target/Mips/MipsDSPInstrFormats.td stable/11/contrib/llvm/lib/Target/Mips/MipsFastISel.cpp stable/11/contrib/llvm/lib/Target/Mips/MipsISelLowering.cpp stable/11/contrib/llvm/lib/Target/Mips/MipsInstrFormats.td stable/11/contrib/llvm/lib/Target/Mips/MipsInstrInfo.cpp stable/11/contrib/llvm/lib/Target/Mips/MipsInstrInfo.td stable/11/contrib/llvm/lib/Target/Mips/MipsLongBranch.cpp stable/11/contrib/llvm/lib/Target/Mips/MipsSEISelLowering.cpp stable/11/contrib/llvm/lib/Target/Mips/MipsSubtarget.cpp stable/11/contrib/llvm/lib/Target/Mips/MipsSubtarget.h stable/11/contrib/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp stable/11/contrib/llvm/lib/Target/PowerPC/PPCISelLowering.cpp stable/11/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp stable/11/contrib/llvm/lib/Target/X86/X86DomainReassignment.cpp stable/11/contrib/llvm/lib/Target/X86/X86FastISel.cpp stable/11/contrib/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp stable/11/contrib/llvm/lib/Target/X86/X86InstrArithmetic.td stable/11/contrib/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp stable/11/contrib/llvm/lib/Transforms/IPO/DeadArgumentElimination.cpp stable/11/contrib/llvm/lib/Transforms/IPO/GlobalOpt.cpp stable/11/contrib/llvm/lib/Transforms/IPO/MergeFunctions.cpp stable/11/contrib/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp stable/11/contrib/llvm/lib/Transforms/Scalar/CallSiteSplitting.cpp stable/11/contrib/llvm/lib/Transforms/Scalar/DivRemPairs.cpp stable/11/contrib/llvm/lib/Transforms/Scalar/JumpThreading.cpp stable/11/contrib/llvm/lib/Transforms/Scalar/SCCP.cpp stable/11/contrib/llvm/lib/Transforms/Utils/FunctionComparator.cpp stable/11/contrib/llvm/tools/clang/include/clang/Basic/DiagnosticDriverKinds.td stable/11/contrib/llvm/tools/clang/include/clang/Basic/DiagnosticSemaKinds.td stable/11/contrib/llvm/tools/clang/include/clang/Driver/CLCompatOptions.td stable/11/contrib/llvm/tools/clang/include/clang/Driver/Options.td stable/11/contrib/llvm/tools/clang/lib/AST/ExprConstant.cpp stable/11/contrib/llvm/tools/clang/lib/AST/RecordLayoutBuilder.cpp stable/11/contrib/llvm/tools/clang/lib/Basic/Targets/AArch64.cpp stable/11/contrib/llvm/tools/clang/lib/Basic/Targets/Mips.h stable/11/contrib/llvm/tools/clang/lib/Basic/Version.cpp stable/11/contrib/llvm/tools/clang/lib/CodeGen/TargetInfo.cpp stable/11/contrib/llvm/tools/clang/lib/Driver/Driver.cpp stable/11/contrib/llvm/tools/clang/lib/Driver/ToolChains/Arch/Mips.cpp stable/11/contrib/llvm/tools/clang/lib/Driver/ToolChains/Arch/Mips.h stable/11/contrib/llvm/tools/clang/lib/Driver/ToolChains/Clang.cpp stable/11/contrib/llvm/tools/clang/lib/Driver/ToolChains/CrossWindows.cpp stable/11/contrib/llvm/tools/clang/lib/Driver/ToolChains/MinGW.cpp stable/11/contrib/llvm/tools/clang/lib/Frontend/ASTUnit.cpp stable/11/contrib/llvm/tools/clang/lib/Frontend/CompilerInvocation.cpp stable/11/contrib/llvm/tools/clang/lib/Headers/avx512vlbitalgintrin.h stable/11/contrib/llvm/tools/clang/lib/Headers/avx512vlvbmi2intrin.h stable/11/contrib/llvm/tools/clang/lib/Headers/avx512vlvnniintrin.h stable/11/contrib/llvm/tools/clang/lib/Sema/SemaDecl.cpp stable/11/contrib/llvm/tools/clang/tools/driver/driver.cpp stable/11/contrib/llvm/tools/lld/COFF/Config.h stable/11/contrib/llvm/tools/lld/COFF/Driver.cpp stable/11/contrib/llvm/tools/lld/COFF/DriverUtils.cpp stable/11/contrib/llvm/tools/lld/COFF/Options.td stable/11/contrib/llvm/tools/lld/ELF/Arch/Mips.cpp stable/11/contrib/llvm/tools/lld/ELF/Config.h stable/11/contrib/llvm/tools/lld/ELF/Driver.cpp stable/11/etc/mtree/BSD.debug.dist stable/11/etc/mtree/BSD.usr.dist stable/11/lib/clang/freebsd_cc_version.h stable/11/lib/clang/headers/Makefile stable/11/lib/clang/include/clang/Basic/Version.inc stable/11/lib/clang/include/clang/Config/config.h stable/11/lib/clang/include/lld/Common/Version.inc stable/11/lib/clang/include/llvm/Config/config.h stable/11/lib/clang/include/llvm/Config/llvm-config.h stable/11/lib/clang/include/llvm/Support/VCSRevision.h stable/11/lib/libclang_rt/Makefile.inc stable/11/tools/build/mk/OptionalObsoleteFiles.inc Directory Properties: stable/11/ (props changed) Modified: stable/11/ObsoleteFiles.inc ============================================================================== --- stable/11/ObsoleteFiles.inc Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/ObsoleteFiles.inc Sat Jul 14 14:20:30 2018 (r336278) @@ -38,6 +38,142 @@ # xargs -n1 | sort | uniq -d; # done +# 20180714: new clang import which bumps version from 6.0.0 to 6.0.1. +OLD_FILES+=usr/lib/clang/6.0.0/include/sanitizer/allocator_interface.h +OLD_FILES+=usr/lib/clang/6.0.0/include/sanitizer/asan_interface.h +OLD_FILES+=usr/lib/clang/6.0.0/include/sanitizer/common_interface_defs.h +OLD_FILES+=usr/lib/clang/6.0.0/include/sanitizer/coverage_interface.h +OLD_FILES+=usr/lib/clang/6.0.0/include/sanitizer/dfsan_interface.h +OLD_FILES+=usr/lib/clang/6.0.0/include/sanitizer/esan_interface.h +OLD_FILES+=usr/lib/clang/6.0.0/include/sanitizer/hwasan_interface.h +OLD_FILES+=usr/lib/clang/6.0.0/include/sanitizer/linux_syscall_hooks.h +OLD_FILES+=usr/lib/clang/6.0.0/include/sanitizer/lsan_interface.h +OLD_FILES+=usr/lib/clang/6.0.0/include/sanitizer/msan_interface.h +OLD_FILES+=usr/lib/clang/6.0.0/include/sanitizer/scudo_interface.h +OLD_FILES+=usr/lib/clang/6.0.0/include/sanitizer/tsan_interface.h +OLD_FILES+=usr/lib/clang/6.0.0/include/sanitizer/tsan_interface_atomic.h +OLD_DIRS+=usr/lib/clang/6.0.0/include/sanitizer +OLD_FILES+=usr/lib/clang/6.0.0/include/__clang_cuda_builtin_vars.h +OLD_FILES+=usr/lib/clang/6.0.0/include/__clang_cuda_cmath.h +OLD_FILES+=usr/lib/clang/6.0.0/include/__clang_cuda_complex_builtins.h +OLD_FILES+=usr/lib/clang/6.0.0/include/__clang_cuda_intrinsics.h +OLD_FILES+=usr/lib/clang/6.0.0/include/__clang_cuda_math_forward_declares.h +OLD_FILES+=usr/lib/clang/6.0.0/include/__clang_cuda_runtime_wrapper.h +OLD_FILES+=usr/lib/clang/6.0.0/include/__stddef_max_align_t.h +OLD_FILES+=usr/lib/clang/6.0.0/include/__wmmintrin_aes.h +OLD_FILES+=usr/lib/clang/6.0.0/include/__wmmintrin_pclmul.h +OLD_FILES+=usr/lib/clang/6.0.0/include/adxintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/altivec.h +OLD_FILES+=usr/lib/clang/6.0.0/include/ammintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/arm64intr.h +OLD_FILES+=usr/lib/clang/6.0.0/include/arm_acle.h +OLD_FILES+=usr/lib/clang/6.0.0/include/arm_neon.h +OLD_FILES+=usr/lib/clang/6.0.0/include/armintr.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx2intrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx512bitalgintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx512bwintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx512cdintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx512dqintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx512erintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx512fintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx512ifmaintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx512ifmavlintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx512pfintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx512vbmi2intrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx512vbmiintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx512vbmivlintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx512vlbitalgintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx512vlbwintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx512vlcdintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx512vldqintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx512vlintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx512vlvbmi2intrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx512vlvnniintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx512vnniintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx512vpopcntdqintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avx512vpopcntdqvlintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/avxintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/bmi2intrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/bmiintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/cetintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/clflushoptintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/clwbintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/clzerointrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/cpuid.h +OLD_FILES+=usr/lib/clang/6.0.0/include/emmintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/f16cintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/fma4intrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/fmaintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/fxsrintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/gfniintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/htmintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/htmxlintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/ia32intrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/immintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/lwpintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/lzcntintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/mm3dnow.h +OLD_FILES+=usr/lib/clang/6.0.0/include/mm_malloc.h +OLD_FILES+=usr/lib/clang/6.0.0/include/mmintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/module.modulemap +OLD_FILES+=usr/lib/clang/6.0.0/include/msa.h +OLD_FILES+=usr/lib/clang/6.0.0/include/mwaitxintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/nmmintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/opencl-c.h +OLD_FILES+=usr/lib/clang/6.0.0/include/pkuintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/pmmintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/popcntintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/prfchwintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/rdseedintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/rtmintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/s390intrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/shaintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/smmintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/tbmintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/tmmintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/vadefs.h +OLD_FILES+=usr/lib/clang/6.0.0/include/vaesintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/vecintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/vpclmulqdqintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/wmmintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/x86intrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/xmmintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/xopintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/xsavecintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/xsaveintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/xsaveoptintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/xsavesintrin.h +OLD_FILES+=usr/lib/clang/6.0.0/include/xtestintrin.h +OLD_DIRS+=usr/lib/clang/6.0.0/include +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.asan-i386.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.asan-i386.so +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.asan-preinit-i386.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.asan-preinit-x86_64.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.asan-x86_64.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.asan-x86_64.so +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.asan_cxx-i386.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.asan_cxx-x86_64.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.profile-arm.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.profile-armhf.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.profile-i386.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.profile-x86_64.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.safestack-i386.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.safestack-x86_64.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.stats-i386.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.stats-x86_64.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.stats_client-i386.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.stats_client-x86_64.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.tsan-x86_64.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.tsan_cxx-x86_64.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.ubsan_minimal-i386.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.ubsan_minimal-x86_64.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.ubsan_standalone-i386.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.ubsan_standalone-x86_64.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.ubsan_standalone_cxx-i386.a +OLD_FILES+=usr/lib/clang/6.0.0/lib/freebsd/libclang_rt.ubsan_standalone_cxx-x86_64.a +OLD_DIRS+=usr/lib/clang/6.0.0/lib/freebsd +OLD_DIRS+=usr/lib/clang/6.0.0/lib +OLD_DIRS+=usr/lib/clang/6.0.0 # 20180613: obsolete libc++ files missed from the 5.0.0 import OLD_FILES+=usr/include/c++/v1/__refstring OLD_FILES+=usr/include/c++/v1/__undef_min_max Modified: stable/11/UPDATING ============================================================================== --- stable/11/UPDATING Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/UPDATING Sat Jul 14 14:20:30 2018 (r336278) @@ -16,6 +16,12 @@ from older versions of FreeBSD, try WITHOUT_CLANG and the tip of head, and then rebuild without this option. The bootstrap process from older version of current across the gcc/clang cutover is a bit fragile. +20180714: + Clang, llvm, lld, lldb, compiler-rt and libc++ have been upgraded to + 6.0.1. Please see the 20141231 entry below for information about + prerequisites and upgrading, if you are not already using clang 3.5.0 + or higher. + 20180504: The tz database (tzdb) has been updated to 2018e. This version more correctly models time stamps in time zones with negative DST such as Modified: stable/11/contrib/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cc ============================================================================== --- stable/11/contrib/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cc Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cc Sat Jul 14 14:20:30 2018 (r336278) @@ -159,7 +159,6 @@ typedef struct user_fpregs elf_fpregset_t; # include <sys/procfs.h> #endif #include <sys/user.h> -#include <sys/ustat.h> #include <linux/cyclades.h> #include <linux/if_eql.h> #include <linux/if_plip.h> @@ -253,7 +252,19 @@ namespace __sanitizer { #endif // SANITIZER_LINUX || SANITIZER_FREEBSD #if SANITIZER_LINUX && !SANITIZER_ANDROID - unsigned struct_ustat_sz = sizeof(struct ustat); + // Use pre-computed size of struct ustat to avoid <sys/ustat.h> which + // has been removed from glibc 2.28. +#if defined(__aarch64__) || defined(__s390x__) || defined (__mips64) \ + || defined(__powerpc64__) || defined(__arch64__) || defined(__sparcv9) \ + || defined(__x86_64__) +#define SIZEOF_STRUCT_USTAT 32 +#elif defined(__arm__) || defined(__i386__) || defined(__mips__) \ + || defined(__powerpc__) || defined(__s390__) +#define SIZEOF_STRUCT_USTAT 20 +#else +#error Unknown size of struct ustat +#endif + unsigned struct_ustat_sz = SIZEOF_STRUCT_USTAT; unsigned struct_rlimit64_sz = sizeof(struct rlimit64); unsigned struct_statvfs64_sz = sizeof(struct statvfs64); #endif // SANITIZER_LINUX && !SANITIZER_ANDROID Modified: stable/11/contrib/libc++/include/list ============================================================================== --- stable/11/contrib/libc++/include/list Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/libc++/include/list Sat Jul 14 14:20:30 2018 (r336278) @@ -2058,15 +2058,15 @@ list<_Tp, _Alloc>::splice(const_iterator __p, list& __ #endif if (__f != __l) { + __link_pointer __first = __f.__ptr_; + --__l; + __link_pointer __last = __l.__ptr_; if (this != &__c) { - size_type __s = _VSTD::distance(__f, __l); + size_type __s = _VSTD::distance(__f, __l) + 1; __c.__sz() -= __s; base::__sz() += __s; } - __link_pointer __first = __f.__ptr_; - --__l; - __link_pointer __last = __l.__ptr_; base::__unlink_nodes(__first, __last); __link_nodes(__p.__ptr_, __first, __last); #if _LIBCPP_DEBUG_LEVEL >= 2 Modified: stable/11/contrib/libc++/src/support/runtime/exception_libcxxabi.ipp ============================================================================== --- stable/11/contrib/libc++/src/support/runtime/exception_libcxxabi.ipp Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/libc++/src/support/runtime/exception_libcxxabi.ipp Sat Jul 14 14:20:30 2018 (r336278) @@ -18,7 +18,7 @@ bool uncaught_exception() _NOEXCEPT { return uncaught_ int uncaught_exceptions() _NOEXCEPT { -# if _LIBCPPABI_VERSION > 1101 +# if _LIBCPPABI_VERSION > 1001 return __cxa_uncaught_exceptions(); # else return __cxa_uncaught_exception() ? 1 : 0; Modified: stable/11/contrib/llvm/include/llvm/CodeGen/TargetInstrInfo.h ============================================================================== --- stable/11/contrib/llvm/include/llvm/CodeGen/TargetInstrInfo.h Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/include/llvm/CodeGen/TargetInstrInfo.h Sat Jul 14 14:20:30 2018 (r336278) @@ -421,7 +421,8 @@ class TargetInstrInfo : public MCInstrInfo { (public) /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI /// and \p DefIdx. /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of - /// the list is modeled as <Reg:SubReg, SubIdx>. + /// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef + /// flag are not added to this list. /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce /// two elements: /// - %1:sub1, sub0 @@ -446,7 +447,8 @@ class TargetInstrInfo : public MCInstrInfo { (public) /// - %1:sub1, sub0 /// /// \returns true if it is possible to build such an input sequence - /// with the pair \p MI, \p DefIdx. False otherwise. + /// with the pair \p MI, \p DefIdx and the operand has no undef flag set. + /// False otherwise. /// /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike(). /// @@ -465,7 +467,8 @@ class TargetInstrInfo : public MCInstrInfo { (public) /// - InsertedReg: %1:sub1, sub3 /// /// \returns true if it is possible to build such an input sequence - /// with the pair \p MI, \p DefIdx. False otherwise. + /// with the pair \p MI, \p DefIdx and the operand has no undef flag set. + /// False otherwise. /// /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike(). /// Modified: stable/11/contrib/llvm/include/llvm/IR/IntrinsicsPowerPC.td ============================================================================== --- stable/11/contrib/llvm/include/llvm/IR/IntrinsicsPowerPC.td Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/include/llvm/IR/IntrinsicsPowerPC.td Sat Jul 14 14:20:30 2018 (r336278) @@ -36,8 +36,12 @@ let TargetPrefix = "ppc" in { // All intrinsics start // Intrinsics used to generate ctr-based loops. These should only be // generated by the PowerPC backend! + // The branch intrinsic is marked as NoDuplicate because loop rotation will + // attempt to duplicate it forming loops where a block reachable from one + // instance of it can contain another. def int_ppc_mtctr : Intrinsic<[], [llvm_anyint_ty], []>; - def int_ppc_is_decremented_ctr_nonzero : Intrinsic<[llvm_i1_ty], [], []>; + def int_ppc_is_decremented_ctr_nonzero : + Intrinsic<[llvm_i1_ty], [], [IntrNoDuplicate]>; // Intrinsics for [double]word extended forms of divide instructions def int_ppc_divwe : GCCBuiltin<"__builtin_divwe">, Modified: stable/11/contrib/llvm/lib/Analysis/GlobalsModRef.cpp ============================================================================== --- stable/11/contrib/llvm/lib/Analysis/GlobalsModRef.cpp Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/Analysis/GlobalsModRef.cpp Sat Jul 14 14:20:30 2018 (r336278) @@ -502,6 +502,8 @@ void GlobalsAAResult::AnalyzeCallGraph(CallGraph &CG, } FunctionInfo &FI = FunctionInfos[F]; + Handles.emplace_front(*this, F); + Handles.front().I = Handles.begin(); bool KnowNothing = false; // Collect the mod/ref properties due to called functions. We only compute Modified: stable/11/contrib/llvm/lib/Analysis/MemorySSA.cpp ============================================================================== --- stable/11/contrib/llvm/lib/Analysis/MemorySSA.cpp Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/Analysis/MemorySSA.cpp Sat Jul 14 14:20:30 2018 (r336278) @@ -153,9 +153,14 @@ class MemoryLocOrCall { (public) if (IsCall != Other.IsCall) return false; - if (IsCall) - return CS.getCalledValue() == Other.CS.getCalledValue(); - return Loc == Other.Loc; + if (!IsCall) + return Loc == Other.Loc; + + if (CS.getCalledValue() != Other.CS.getCalledValue()) + return false; + + return CS.arg_size() == Other.CS.arg_size() && + std::equal(CS.arg_begin(), CS.arg_end(), Other.CS.arg_begin()); } private: @@ -179,12 +184,18 @@ template <> struct DenseMapInfo<MemoryLocOrCall> { } static unsigned getHashValue(const MemoryLocOrCall &MLOC) { - if (MLOC.IsCall) - return hash_combine(MLOC.IsCall, - DenseMapInfo<const Value *>::getHashValue( - MLOC.getCS().getCalledValue())); - return hash_combine( - MLOC.IsCall, DenseMapInfo<MemoryLocation>::getHashValue(MLOC.getLoc())); + if (!MLOC.IsCall) + return hash_combine( + MLOC.IsCall, + DenseMapInfo<MemoryLocation>::getHashValue(MLOC.getLoc())); + + hash_code hash = + hash_combine(MLOC.IsCall, DenseMapInfo<const Value *>::getHashValue( + MLOC.getCS().getCalledValue())); + + for (const Value *Arg : MLOC.getCS().args()) + hash = hash_combine(hash, DenseMapInfo<const Value *>::getHashValue(Arg)); + return hash; } static bool isEqual(const MemoryLocOrCall &LHS, const MemoryLocOrCall &RHS) { Modified: stable/11/contrib/llvm/lib/CodeGen/IfConversion.cpp ============================================================================== --- stable/11/contrib/llvm/lib/CodeGen/IfConversion.cpp Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/CodeGen/IfConversion.cpp Sat Jul 14 14:20:30 2018 (r336278) @@ -1714,20 +1714,25 @@ bool IfConverter::IfConvertDiamondCommon( } // Remove the duplicated instructions at the beginnings of both paths. - // Skip dbg_value instructions + // Skip dbg_value instructions. MachineBasicBlock::iterator DI1 = MBB1.getFirstNonDebugInstr(); MachineBasicBlock::iterator DI2 = MBB2.getFirstNonDebugInstr(); BBI1->NonPredSize -= NumDups1; BBI2->NonPredSize -= NumDups1; // Skip past the dups on each side separately since there may be - // differing dbg_value entries. + // differing dbg_value entries. NumDups1 can include a "return" + // instruction, if it's not marked as "branch". for (unsigned i = 0; i < NumDups1; ++DI1) { + if (DI1 == MBB1.end()) + break; if (!DI1->isDebugValue()) ++i; } while (NumDups1 != 0) { ++DI2; + if (DI2 == MBB2.end()) + break; if (!DI2->isDebugValue()) --NumDups1; } @@ -1738,11 +1743,16 @@ bool IfConverter::IfConvertDiamondCommon( Redefs.stepForward(MI, Dummy); } } + BBI.BB->splice(BBI.BB->end(), &MBB1, MBB1.begin(), DI1); MBB2.erase(MBB2.begin(), DI2); - // The branches have been checked to match, so it is safe to remove the branch - // in BB1 and rely on the copy in BB2 + // The branches have been checked to match, so it is safe to remove the + // branch in BB1 and rely on the copy in BB2. The complication is that + // the blocks may end with a return instruction, which may or may not + // be marked as "branch". If it's not, then it could be included in + // "dups1", leaving the blocks potentially empty after moving the common + // duplicates. #ifndef NDEBUG // Unanalyzable branches must match exactly. Check that now. if (!BBI1->IsBrAnalyzable) @@ -1768,11 +1778,14 @@ bool IfConverter::IfConvertDiamondCommon( if (RemoveBranch) BBI2->NonPredSize -= TII->removeBranch(*BBI2->BB); else { - do { - assert(DI2 != MBB2.begin()); - DI2--; - } while (DI2->isBranch() || DI2->isDebugValue()); - DI2++; + // Make DI2 point to the end of the range where the common "tail" + // instructions could be found. + while (DI2 != MBB2.begin()) { + MachineBasicBlock::iterator Prev = std::prev(DI2); + if (!Prev->isBranch() && !Prev->isDebugValue()) + break; + DI2 = Prev; + } } while (NumDups2 != 0) { // NumDups2 only counted non-dbg_value instructions, so this won't @@ -1833,11 +1846,15 @@ bool IfConverter::IfConvertDiamondCommon( // a non-predicated in BBI2, then we don't want to predicate the one from // BBI2. The reason is that if we merged these blocks, we would end up with // two predicated terminators in the same block. + // Also, if the branches in MBB1 and MBB2 were non-analyzable, then don't + // predicate them either. They were checked to be identical, and so the + // same branch would happen regardless of which path was taken. if (!MBB2.empty() && (DI2 == MBB2.end())) { MachineBasicBlock::iterator BBI1T = MBB1.getFirstTerminator(); MachineBasicBlock::iterator BBI2T = MBB2.getFirstTerminator(); - if (BBI1T != MBB1.end() && TII->isPredicated(*BBI1T) && - BBI2T != MBB2.end() && !TII->isPredicated(*BBI2T)) + bool BB1Predicated = BBI1T != MBB1.end() && TII->isPredicated(*BBI1T); + bool BB2NonPredicated = BBI2T != MBB2.end() && !TII->isPredicated(*BBI2T); + if (BB2NonPredicated && (BB1Predicated || !BBI2->IsBrAnalyzable)) --DI2; } Modified: stable/11/contrib/llvm/lib/CodeGen/LiveDebugVariables.cpp ============================================================================== --- stable/11/contrib/llvm/lib/CodeGen/LiveDebugVariables.cpp Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/CodeGen/LiveDebugVariables.cpp Sat Jul 14 14:20:30 2018 (r336278) @@ -514,6 +514,39 @@ bool LDVImpl::handleDebugValue(MachineInstr &MI, SlotI return false; } + // Detect invalid DBG_VALUE instructions, with a debug-use of a virtual + // register that hasn't been defined yet. If we do not remove those here, then + // the re-insertion of the DBG_VALUE instruction after register allocation + // will be incorrect. + // TODO: If earlier passes are corrected to generate sane debug information + // (and if the machine verifier is improved to catch this), then these checks + // could be removed or replaced by asserts. + bool Discard = false; + if (MI.getOperand(0).isReg() && + TargetRegisterInfo::isVirtualRegister(MI.getOperand(0).getReg())) { + const unsigned Reg = MI.getOperand(0).getReg(); + if (!LIS->hasInterval(Reg)) { + // The DBG_VALUE is described by a virtual register that does not have a + // live interval. Discard the DBG_VALUE. + Discard = true; + DEBUG(dbgs() << "Discarding debug info (no LIS interval): " + << Idx << " " << MI); + } else { + // The DBG_VALUE is only valid if either Reg is live out from Idx, or Reg + // is defined dead at Idx (where Idx is the slot index for the instruction + // preceeding the DBG_VALUE). + const LiveInterval &LI = LIS->getInterval(Reg); + LiveQueryResult LRQ = LI.Query(Idx); + if (!LRQ.valueOutOrDead()) { + // We have found a DBG_VALUE with the value in a virtual register that + // is not live. Discard the DBG_VALUE. + Discard = true; + DEBUG(dbgs() << "Discarding debug info (reg not live): " + << Idx << " " << MI); + } + } + } + // Get or create the UserValue for (variable,offset) here. bool IsIndirect = MI.getOperand(1).isImm(); if (IsIndirect) @@ -522,7 +555,13 @@ bool LDVImpl::handleDebugValue(MachineInstr &MI, SlotI const DIExpression *Expr = MI.getDebugExpression(); UserValue *UV = getUserValue(Var, Expr, MI.getDebugLoc()); - UV->addDef(Idx, MI.getOperand(0), IsIndirect); + if (!Discard) + UV->addDef(Idx, MI.getOperand(0), IsIndirect); + else { + MachineOperand MO = MachineOperand::CreateReg(0U, false); + MO.setIsDebug(); + UV->addDef(Idx, MO, false); + } return true; } Modified: stable/11/contrib/llvm/lib/CodeGen/MachineBlockPlacement.cpp ============================================================================== --- stable/11/contrib/llvm/lib/CodeGen/MachineBlockPlacement.cpp Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/CodeGen/MachineBlockPlacement.cpp Sat Jul 14 14:20:30 2018 (r336278) @@ -513,6 +513,11 @@ class MachineBlockPlacement : public MachineFunctionPa bool runOnMachineFunction(MachineFunction &F) override; + bool allowTailDupPlacement() const { + assert(F); + return TailDupPlacement && !F->getTarget().requiresStructuredCFG(); + } + void getAnalysisUsage(AnalysisUsage &AU) const override { AU.addRequired<MachineBranchProbabilityInfo>(); AU.addRequired<MachineBlockFrequencyInfo>(); @@ -1018,7 +1023,7 @@ MachineBlockPlacement::getBestTrellisSuccessor( MachineBasicBlock *Succ1 = BestA.Dest; MachineBasicBlock *Succ2 = BestB.Dest; // Check to see if tail-duplication would be profitable. - if (TailDupPlacement && shouldTailDuplicate(Succ2) && + if (allowTailDupPlacement() && shouldTailDuplicate(Succ2) && canTailDuplicateUnplacedPreds(BB, Succ2, Chain, BlockFilter) && isProfitableToTailDup(BB, Succ2, MBPI->getEdgeProbability(BB, Succ1), Chain, BlockFilter)) { @@ -1044,7 +1049,7 @@ MachineBlockPlacement::getBestTrellisSuccessor( return Result; } -/// When the option TailDupPlacement is on, this method checks if the +/// When the option allowTailDupPlacement() is on, this method checks if the /// fallthrough candidate block \p Succ (of block \p BB) can be tail-duplicated /// into all of its unplaced, unfiltered predecessors, that are not BB. bool MachineBlockPlacement::canTailDuplicateUnplacedPreds( @@ -1493,7 +1498,7 @@ MachineBlockPlacement::selectBestSuccessor( if (hasBetterLayoutPredecessor(BB, Succ, SuccChain, SuccProb, RealSuccProb, Chain, BlockFilter)) { // If tail duplication would make Succ profitable, place it. - if (TailDupPlacement && shouldTailDuplicate(Succ)) + if (allowTailDupPlacement() && shouldTailDuplicate(Succ)) DupCandidates.push_back(std::make_tuple(SuccProb, Succ)); continue; } @@ -1702,7 +1707,7 @@ void MachineBlockPlacement::buildChain( auto Result = selectBestSuccessor(BB, Chain, BlockFilter); MachineBasicBlock* BestSucc = Result.BB; bool ShouldTailDup = Result.ShouldTailDup; - if (TailDupPlacement) + if (allowTailDupPlacement()) ShouldTailDup |= (BestSucc && shouldTailDuplicate(BestSucc)); // If an immediate successor isn't available, look for the best viable @@ -1724,7 +1729,7 @@ void MachineBlockPlacement::buildChain( // Placement may have changed tail duplication opportunities. // Check for that now. - if (TailDupPlacement && BestSucc && ShouldTailDup) { + if (allowTailDupPlacement() && BestSucc && ShouldTailDup) { // If the chosen successor was duplicated into all its predecessors, // don't bother laying it out, just go round the loop again with BB as // the chain end. @@ -2758,7 +2763,7 @@ bool MachineBlockPlacement::runOnMachineFunction(Machi TailDupSize = TailDupPlacementAggressiveThreshold; } - if (TailDupPlacement) { + if (allowTailDupPlacement()) { MPDT = &getAnalysis<MachinePostDominatorTree>(); if (MF.getFunction().optForSize()) TailDupSize = 1; Modified: stable/11/contrib/llvm/lib/CodeGen/PeepholeOptimizer.cpp ============================================================================== --- stable/11/contrib/llvm/lib/CodeGen/PeepholeOptimizer.cpp Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/CodeGen/PeepholeOptimizer.cpp Sat Jul 14 14:20:30 2018 (r336278) @@ -1812,6 +1812,8 @@ ValueTrackerResult ValueTracker::getNextSourceFromCopy return ValueTrackerResult(); // Otherwise, we want the whole source. const MachineOperand &Src = Def->getOperand(1); + if (Src.isUndef()) + return ValueTrackerResult(); return ValueTrackerResult(Src.getReg(), Src.getSubReg()); } @@ -1855,6 +1857,8 @@ ValueTrackerResult ValueTracker::getNextSourceFromBitc } const MachineOperand &Src = Def->getOperand(SrcIdx); + if (Src.isUndef()) + return ValueTrackerResult(); return ValueTrackerResult(Src.getReg(), Src.getSubReg()); } @@ -2023,6 +2027,10 @@ ValueTrackerResult ValueTracker::getNextSourceFromPHI( for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) { const MachineOperand &MO = Def->getOperand(i); assert(MO.isReg() && "Invalid PHI instruction"); + // We have no code to deal with undef operands. They shouldn't happen in + // normal programs anyway. + if (MO.isUndef()) + return ValueTrackerResult(); Res.addSource(MO.getReg(), MO.getSubReg()); } @@ -2079,9 +2087,14 @@ ValueTrackerResult ValueTracker::getNextSource() { // If we can still move up in the use-def chain, move to the next // definition. if (!TargetRegisterInfo::isPhysicalRegister(Reg) && OneRegSrc) { - Def = MRI.getVRegDef(Reg); - DefIdx = MRI.def_begin(Reg).getOperandNo(); - DefSubReg = Res.getSrcSubReg(0); + MachineRegisterInfo::def_iterator DI = MRI.def_begin(Reg); + if (DI != MRI.def_end()) { + Def = DI->getParent(); + DefIdx = DI.getOperandNo(); + DefSubReg = Res.getSrcSubReg(0); + } else { + Def = nullptr; + } return Res; } } Modified: stable/11/contrib/llvm/lib/CodeGen/TargetInstrInfo.cpp ============================================================================== --- stable/11/contrib/llvm/lib/CodeGen/TargetInstrInfo.cpp Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/CodeGen/TargetInstrInfo.cpp Sat Jul 14 14:20:30 2018 (r336278) @@ -1151,6 +1151,8 @@ bool TargetInstrInfo::getRegSequenceInputs( for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx; OpIdx += 2) { const MachineOperand &MOReg = MI.getOperand(OpIdx); + if (MOReg.isUndef()) + continue; const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1); assert(MOSubIdx.isImm() && "One of the subindex of the reg_sequence is not an immediate"); @@ -1174,6 +1176,8 @@ bool TargetInstrInfo::getExtractSubregInputs( // Def = EXTRACT_SUBREG v0.sub1, sub0. assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def"); const MachineOperand &MOReg = MI.getOperand(1); + if (MOReg.isUndef()) + return false; const MachineOperand &MOSubIdx = MI.getOperand(2); assert(MOSubIdx.isImm() && "The subindex of the extract_subreg is not an immediate"); @@ -1198,6 +1202,8 @@ bool TargetInstrInfo::getInsertSubregInputs( assert(DefIdx == 0 && "INSERT_SUBREG only has one def"); const MachineOperand &MOBaseReg = MI.getOperand(1); const MachineOperand &MOInsertedReg = MI.getOperand(2); + if (MOInsertedReg.isUndef()) + return false; const MachineOperand &MOSubIdx = MI.getOperand(3); assert(MOSubIdx.isImm() && "One of the subindex of the reg_sequence is not an immediate"); Modified: stable/11/contrib/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp ============================================================================== --- stable/11/contrib/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp Sat Jul 14 14:20:30 2018 (r336278) @@ -1422,7 +1422,8 @@ RuntimeDyldELF::processRelocationRef( SectionEntry &Section = Sections[SectionID]; uint8_t *Target = Section.getAddressWithOffset(Offset); bool RangeOverflow = false; - if (!Value.SymbolName && SymType != SymbolRef::ST_Unknown) { + bool IsExtern = Value.SymbolName || SymType == SymbolRef::ST_Unknown; + if (!IsExtern) { if (AbiVariant != 2) { // In the ELFv1 ABI, a function call may point to the .opd entry, // so the final symbol value is calculated based on the relocation @@ -1432,21 +1433,24 @@ RuntimeDyldELF::processRelocationRef( } else { // In the ELFv2 ABI, a function symbol may provide a local entry // point, which must be used for direct calls. - uint8_t SymOther = Symbol->getOther(); - Value.Addend += ELF::decodePPC64LocalEntryOffset(SymOther); + if (Value.SectionID == SectionID){ + uint8_t SymOther = Symbol->getOther(); + Value.Addend += ELF::decodePPC64LocalEntryOffset(SymOther); + } } uint8_t *RelocTarget = Sections[Value.SectionID].getAddressWithOffset(Value.Addend); int64_t delta = static_cast<int64_t>(Target - RelocTarget); // If it is within 26-bits branch range, just set the branch target - if (SignExtend64<26>(delta) == delta) { + if (SignExtend64<26>(delta) != delta) { + RangeOverflow = true; + } else if ((AbiVariant != 2) || + (AbiVariant == 2 && Value.SectionID == SectionID)) { RelocationEntry RE(SectionID, Offset, RelType, Value.Addend); addRelocationForSection(RE, Value.SectionID); - } else { - RangeOverflow = true; } } - if (Value.SymbolName || SymType == SymbolRef::ST_Unknown || + if (IsExtern || (AbiVariant == 2 && Value.SectionID != SectionID) || RangeOverflow) { // It is an external symbol (either Value.SymbolName is set, or // SymType is SymbolRef::ST_Unknown) or out of range. @@ -1503,10 +1507,10 @@ RuntimeDyldELF::processRelocationRef( RelType, 0); Section.advanceStubOffset(getMaxStubSize()); } - if (Value.SymbolName || SymType == SymbolRef::ST_Unknown) { + if (IsExtern || (AbiVariant == 2 && Value.SectionID != SectionID)) { // Restore the TOC for external calls if (AbiVariant == 2) - writeInt32BE(Target + 4, 0xE8410018); // ld r2,28(r1) + writeInt32BE(Target + 4, 0xE8410018); // ld r2,24(r1) else writeInt32BE(Target + 4, 0xE8410028); // ld r2,40(r1) } Modified: stable/11/contrib/llvm/lib/IR/Core.cpp ============================================================================== --- stable/11/contrib/llvm/lib/IR/Core.cpp Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/IR/Core.cpp Sat Jul 14 14:20:30 2018 (r336278) @@ -359,11 +359,9 @@ LLVMContextRef LLVMGetTypeContext(LLVMTypeRef Ty) { return wrap(&unwrap(Ty)->getContext()); } -#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) -LLVM_DUMP_METHOD void LLVMDumpType(LLVMTypeRef Ty) { - return unwrap(Ty)->dump(); +void LLVMDumpType(LLVMTypeRef Ty) { + return unwrap(Ty)->print(errs(), /*IsForDebug=*/true); } -#endif char *LLVMPrintTypeToString(LLVMTypeRef Ty) { std::string buf; @@ -658,7 +656,7 @@ void LLVMSetValueName(LLVMValueRef Val, const char *Na unwrap(Val)->setName(Name); } -LLVM_DUMP_METHOD void LLVMDumpValue(LLVMValueRef Val) { +void LLVMDumpValue(LLVMValueRef Val) { unwrap(Val)->print(errs(), /*IsForDebug=*/true); } Modified: stable/11/contrib/llvm/lib/MC/MCObjectFileInfo.cpp ============================================================================== --- stable/11/contrib/llvm/lib/MC/MCObjectFileInfo.cpp Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/MC/MCObjectFileInfo.cpp Sat Jul 14 14:20:30 2018 (r336278) @@ -289,6 +289,8 @@ void MCObjectFileInfo::initELFMCObjectFileInfo(const T case Triple::mips64el: FDECFIEncoding = dwarf::DW_EH_PE_sdata8; break; + case Triple::ppc64: + case Triple::ppc64le: case Triple::x86_64: FDECFIEncoding = dwarf::DW_EH_PE_pcrel | (Large ? dwarf::DW_EH_PE_sdata8 : dwarf::DW_EH_PE_sdata4); Modified: stable/11/contrib/llvm/lib/Support/Host.cpp ============================================================================== --- stable/11/contrib/llvm/lib/Support/Host.cpp Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/Support/Host.cpp Sat Jul 14 14:20:30 2018 (r336278) @@ -1009,7 +1009,7 @@ StringRef sys::getHostCPUName() { #include "llvm/Support/X86TargetParser.def" // Now check types. -#define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \ +#define X86_CPU_TYPE(ARCHNAME, ENUM) \ if (Type == X86::ENUM) \ return ARCHNAME; #include "llvm/Support/X86TargetParser.def" Modified: stable/11/contrib/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp ============================================================================== --- stable/11/contrib/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp Sat Jul 14 14:20:30 2018 (r336278) @@ -299,6 +299,11 @@ void AArch64AsmPrinter::printOperand(const MachineInst printOffset(MO.getOffset(), O); break; } + case MachineOperand::MO_BlockAddress: { + MCSymbol *Sym = GetBlockAddressSymbol(MO.getBlockAddress()); + Sym->print(O, MAI); + break; + } } } Modified: stable/11/contrib/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp ============================================================================== --- stable/11/contrib/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp Sat Jul 14 14:20:30 2018 (r336278) @@ -46,6 +46,7 @@ #include "llvm/Pass.h" #include "llvm/Support/Casting.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/DebugCounter.h" #include "llvm/Support/raw_ostream.h" #include <cassert> #include <iterator> @@ -60,6 +61,8 @@ STATISTIC(NumCollisionsAvoided, "Number of HW prefetch tag collisions avoided"); STATISTIC(NumCollisionsNotAvoided, "Number of HW prefetch tag collisions not avoided due to lack of regsiters"); +DEBUG_COUNTER(FixCounter, "falkor-hwpf", + "Controls which tag collisions are avoided"); namespace { @@ -728,6 +731,21 @@ void FalkorHWPFFix::runOnLoop(MachineLoop &L, MachineF bool Fixed = false; DEBUG(dbgs() << "Attempting to fix tag collision: " << MI); + + if (!DebugCounter::shouldExecute(FixCounter)) { + DEBUG(dbgs() << "Skipping fix due to debug counter:\n " << MI); + continue; + } + + // Add the non-base registers of MI as live so we don't use them as + // scratch registers. + for (unsigned OpI = 0, OpE = MI.getNumOperands(); OpI < OpE; ++OpI) { + if (OpI == static_cast<unsigned>(LdI.BaseRegIdx)) + continue; + MachineOperand &MO = MI.getOperand(OpI); + if (MO.isReg() && MO.readsReg()) + LR.addReg(MO.getReg()); + } for (unsigned ScratchReg : AArch64::GPR64RegClass) { if (!LR.available(ScratchReg) || MRI.isReserved(ScratchReg)) Modified: stable/11/contrib/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp ============================================================================== --- stable/11/contrib/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp Sat Jul 14 14:20:30 2018 (r336278) @@ -917,6 +917,8 @@ int AArch64FrameLowering::resolveFrameIndexReference(c int FPOffset = MFI.getObjectOffset(FI) + FixedObject + 16; int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize(); bool isFixed = MFI.isFixedObjectIndex(FI); + bool isCSR = !isFixed && MFI.getObjectOffset(FI) >= + -((int)AFI->getCalleeSavedStackSize()); // Use frame pointer to reference fixed objects. Use it for locals if // there are VLAs or a dynamically realigned SP (and thus the SP isn't @@ -930,6 +932,12 @@ int AArch64FrameLowering::resolveFrameIndexReference(c // Argument access should always use the FP. if (isFixed) { UseFP = hasFP(MF); + } else if (isCSR && RegInfo->needsStackRealignment(MF)) { + // References to the CSR area must use FP if we're re-aligning the stack + // since the dynamically-sized alignment padding is between the SP/BP and + // the CSR area. + assert(hasFP(MF) && "Re-aligned stack must have frame pointer"); + UseFP = true; } else if (hasFP(MF) && !RegInfo->hasBasePointer(MF) && !RegInfo->needsStackRealignment(MF)) { // Use SP or FP, whichever gives us the best chance of the offset @@ -947,9 +955,9 @@ int AArch64FrameLowering::resolveFrameIndexReference(c } } - assert((isFixed || !RegInfo->needsStackRealignment(MF) || !UseFP) && + assert(((isFixed || isCSR) || !RegInfo->needsStackRealignment(MF) || !UseFP) && "In the presence of dynamic stack pointer realignment, " - "non-argument objects cannot be accessed through the frame pointer"); + "non-argument/CSR objects cannot be accessed through the frame pointer"); if (UseFP) { FrameReg = RegInfo->getFrameRegister(MF); Modified: stable/11/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp ============================================================================== --- stable/11/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp Sat Jul 14 14:20:30 2018 (r336278) @@ -4930,7 +4930,8 @@ bool AArch64TargetLowering::isOffsetFoldingLegal( bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases. // FIXME: We should be able to handle f128 as well with a clever lowering. - if (Imm.isPosZero() && (VT == MVT::f16 || VT == MVT::f64 || VT == MVT::f32)) { + if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32 || + (VT == MVT::f16 && Subtarget->hasFullFP16()))) { DEBUG(dbgs() << "Legal fp imm: materialize 0 using the zero register\n"); return true; } @@ -5066,7 +5067,7 @@ SDValue AArch64TargetLowering::getRecipEstimate(SDValu // Table of Constraints // TODO: This is the current set of constraints supported by ARM for the -// compiler, not all of them may make sense, e.g. S may be difficult to support. +// compiler, not all of them may make sense. // // r - A general register // w - An FP/SIMD register of some size in the range v0-v31 @@ -5126,6 +5127,8 @@ AArch64TargetLowering::getConstraintType(StringRef Con // currently handle addresses it is the same as 'r'. case 'Q': return C_Memory; + case 'S': // A symbolic address + return C_Other; } } return TargetLowering::getConstraintType(Constraint); @@ -5250,6 +5253,23 @@ void AArch64TargetLowering::LowerAsmOperandForConstrai Result = DAG.getRegister(AArch64::WZR, MVT::i32); break; } + case 'S': { + // An absolute symbolic address or label reference. + if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) { + Result = DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op), + GA->getValueType(0)); + } else if (const BlockAddressSDNode *BA = + dyn_cast<BlockAddressSDNode>(Op)) { + Result = + DAG.getTargetBlockAddress(BA->getBlockAddress(), BA->getValueType(0)); + } else if (const ExternalSymbolSDNode *ES = + dyn_cast<ExternalSymbolSDNode>(Op)) { + Result = + DAG.getTargetExternalSymbol(ES->getSymbol(), ES->getValueType(0)); + } else + return; + break; + } case 'I': case 'J': @@ -9637,6 +9657,15 @@ static SDValue performPostLD1Combine(SDNode *N, if (LD->getOpcode() != ISD::LOAD) return SDValue(); + // The vector lane must be a constant in the LD1LANE opcode. + SDValue Lane; + if (IsLaneOp) { + Lane = N->getOperand(2); + auto *LaneC = dyn_cast<ConstantSDNode>(Lane); + if (!LaneC || LaneC->getZExtValue() >= VT.getVectorNumElements()) + return SDValue(); + } + LoadSDNode *LoadSDN = cast<LoadSDNode>(LD); EVT MemVT = LoadSDN->getMemoryVT(); // Check if memory operand is the same type as the vector element. @@ -9693,7 +9722,7 @@ static SDValue performPostLD1Combine(SDNode *N, Ops.push_back(LD->getOperand(0)); // Chain if (IsLaneOp) { Ops.push_back(Vector); // The vector to be inserted - Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector + Ops.push_back(Lane); // The lane to be inserted in the vector } Ops.push_back(Addr); Ops.push_back(Inc); Modified: stable/11/contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.td ============================================================================== --- stable/11/contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.td Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.td Sat Jul 14 14:20:30 2018 (r336278) @@ -2713,7 +2713,7 @@ defm FMOV : UnscaledConversion<"fmov">; // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable let isReMaterializable = 1, isCodeGenOnly = 1, isAsCheapAsAMove = 1 in { def FMOVH0 : Pseudo<(outs FPR16:$Rd), (ins), [(set f16:$Rd, (fpimm0))]>, - Sched<[WriteF]>; + Sched<[WriteF]>, Requires<[HasFullFP16]>; def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>, Sched<[WriteF]>; def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>, Modified: stable/11/contrib/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp ============================================================================== --- stable/11/contrib/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp Sat Jul 14 14:20:30 2018 (r336278) @@ -147,6 +147,7 @@ extern "C" void LLVMInitializeAMDGPUTarget() { initializeR600PacketizerPass(*PR); initializeR600ExpandSpecialInstrsPassPass(*PR); initializeR600VectorRegMergerPass(*PR); + initializeGlobalISel(*PR); initializeAMDGPUDAGToDAGISelPass(*PR); initializeSILowerI1CopiesPass(*PR); initializeSIFixSGPRCopiesPass(*PR); Modified: stable/11/contrib/llvm/lib/Target/AMDGPU/SIISelLowering.cpp ============================================================================== --- stable/11/contrib/llvm/lib/Target/AMDGPU/SIISelLowering.cpp Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/Target/AMDGPU/SIISelLowering.cpp Sat Jul 14 14:20:30 2018 (r336278) @@ -358,6 +358,7 @@ SITargetLowering::SITargetLowering(const TargetMachine setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Promote); setOperationAction(ISD::CTLZ, MVT::i16, Promote); setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Promote); + setOperationAction(ISD::CTPOP, MVT::i16, Promote); setOperationAction(ISD::SELECT_CC, MVT::i16, Expand); Modified: stable/11/contrib/llvm/lib/Target/AMDGPU/SIInstructions.td ============================================================================== --- stable/11/contrib/llvm/lib/Target/AMDGPU/SIInstructions.td Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/Target/AMDGPU/SIInstructions.td Sat Jul 14 14:20:30 2018 (r336278) @@ -726,6 +726,10 @@ def : GCNPat < (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)), (V_BCNT_U32_B32_e64 $popcnt, $val) >; +def : GCNPat < + (i16 (add (i16 (trunc (ctpop i32:$popcnt))), i16:$val)), + (V_BCNT_U32_B32_e64 $popcnt, $val) +>; /********** ============================================ **********/ /********** Extraction, Insertion, Building and Casting **********/ Modified: stable/11/contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp ============================================================================== --- stable/11/contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp Sat Jul 14 14:20:30 2018 (r336278) @@ -4864,12 +4864,14 @@ bool ARMBaseInstrInfo::getRegSequenceLikeInputs( // Populate the InputRegs accordingly. // rY const MachineOperand *MOReg = &MI.getOperand(1); - InputRegs.push_back( - RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0)); + if (!MOReg->isUndef()) + InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(), + MOReg->getSubReg(), ARM::ssub_0)); // rZ MOReg = &MI.getOperand(2); - InputRegs.push_back( - RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1)); + if (!MOReg->isUndef()) + InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(), + MOReg->getSubReg(), ARM::ssub_1)); return true; } llvm_unreachable("Target dependent opcode missing"); @@ -4888,6 +4890,8 @@ bool ARMBaseInstrInfo::getExtractSubregLikeInputs( // rX = EXTRACT_SUBREG dZ, ssub_0 // rY = EXTRACT_SUBREG dZ, ssub_1 const MachineOperand &MOReg = MI.getOperand(2); + if (MOReg.isUndef()) + return false; InputReg.Reg = MOReg.getReg(); InputReg.SubReg = MOReg.getSubReg(); InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1; @@ -4907,6 +4911,8 @@ bool ARMBaseInstrInfo::getInsertSubregLikeInputs( // dX = VSETLNi32 dY, rZ, imm const MachineOperand &MOBaseReg = MI.getOperand(1); const MachineOperand &MOInsertedReg = MI.getOperand(2); + if (MOInsertedReg.isUndef()) + return false; const MachineOperand &MOIndex = MI.getOperand(3); BaseReg.Reg = MOBaseReg.getReg(); BaseReg.SubReg = MOBaseReg.getSubReg(); Modified: stable/11/contrib/llvm/lib/Target/ARM/ARMComputeBlockSize.cpp ============================================================================== --- stable/11/contrib/llvm/lib/Target/ARM/ARMComputeBlockSize.cpp Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/Target/ARM/ARMComputeBlockSize.cpp Sat Jul 14 14:20:30 2018 (r336278) @@ -35,6 +35,7 @@ mayOptimizeThumb2Instruction(const MachineInstr *MI) { case ARM::tBcc: // optimizeThumb2JumpTables. case ARM::t2BR_JT: + case ARM::tBR_JTr: return true; } return false; Modified: stable/11/contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp ============================================================================== --- stable/11/contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Sat Jul 14 14:20:30 2018 (r336278) @@ -5136,6 +5136,7 @@ unsigned MipsAsmParser::checkTargetMatchPredicate(MCIn // It also applies for registers Rt and Rs of microMIPSr6 jalrc.hb instruction // and registers Rd and Base for microMIPS lwp instruction case Mips::JALR_HB: + case Mips::JALR_HB64: case Mips::JALRC_HB_MMR6: case Mips::JALRC_MMR6: if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) Modified: stable/11/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp ============================================================================== --- stable/11/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp Sat Jul 14 13:45:31 2018 (r336277) +++ stable/11/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp Sat Jul 14 14:20:30 2018 (r336278) @@ -225,6 +225,8 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext & switch (Kind) { case Mips::fixup_Mips_NONE: return ELF::R_MIPS_NONE; *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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