Date: Thu, 24 May 2018 06:44:06 +0000 (UTC) From: Navdeep Parhar <np@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r334132 - head/sys/dev/cxgbe Message-ID: <201805240644.w4O6i6IF070829@repo.freebsd.org>
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Author: np Date: Thu May 24 06:44:06 2018 New Revision: 334132 URL: https://svnweb.freebsd.org/changeset/base/334132 Log: cxgbe(4): Make sure that the egress queue's cidx is updated periodically when the driver is writing WRs using start_wrq_wr/commit_wrq_wr all the time. Sponsored by: Chelsio Communications Modified: head/sys/dev/cxgbe/t4_sge.c Modified: head/sys/dev/cxgbe/t4_sge.c ============================================================================== --- head/sys/dev/cxgbe/t4_sge.c Thu May 24 04:43:40 2018 (r334131) +++ head/sys/dev/cxgbe/t4_sge.c Thu May 24 06:44:06 2018 (r334132) @@ -2367,9 +2367,29 @@ commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq next = TAILQ_NEXT(cookie, link); if (prev == NULL) { MPASS(pidx == eq->dbidx); - if (next == NULL || ndesc >= 16) + if (next == NULL || ndesc >= 16) { + int available; + struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */ + + /* + * Note that the WR via which we'll request tx updates + * is at pidx and not eq->pidx, which has moved on + * already. + */ + dst = (void *)&eq->desc[pidx]; + available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1; + if (available < eq->sidx / 4 && + atomic_cmpset_int(&eq->equiq, 0, 1)) { + dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ | + F_FW_WR_EQUEQ); + eq->equeqidx = pidx; + } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) { + dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); + eq->equeqidx = pidx; + } + ring_eq_db(wrq->adapter, eq, ndesc); - else { + } else { MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc); next->pidx = pidx; next->ndesc += ndesc;
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