Date: Mon, 2 Sep 2024 09:12:36 GMT From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org Subject: git: 10595e9b2f65 - stable/13 - arm64: Support counter access with E2H Message-ID: <202409020912.4829Cait049486@gitrepo.freebsd.org>
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The branch stable/13 has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=10595e9b2f659693c4e3d486a577c18f1d2e7efe commit 10595e9b2f659693c4e3d486a577c18f1d2e7efe Author: Andrew Turner <andrew@FreeBSD.org> AuthorDate: 2024-07-23 09:18:00 +0000 Commit: Andrew Turner <andrew@FreeBSD.org> CommitDate: 2024-09-02 09:11:57 +0000 arm64: Support counter access with E2H When entering the kernel with the E2H field set the layout of the cnthctl_el2 register changes. Use the correct field locations to enable access to the counter and timer registers from EL1. Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D45529 (cherry picked from commit 997511dffe651e1d2d708f37f2ced430a6ab3349) --- sys/arm64/arm64/locore.S | 6 ++++-- sys/arm64/include/hypervisor.h | 9 +++++++-- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S index 4bde1df945cb..007ffdcae513 100644 --- a/sys/arm64/arm64/locore.S +++ b/sys/arm64/arm64/locore.S @@ -273,8 +273,10 @@ LENTRY(enter_kernel_el) msr hstr_el2, xzr /* Enable access to the physical timers at EL1 */ - mrs x2, cnthctl_el2 - orr x2, x2, #(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN) + tst x4, #HCR_E2H + ldr x3, =(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN) + ldr x5, =(CNTHCTL_E2H_EL1PCTEN | CNTHCTL_E2H_EL1PTEN) + csel x2, x3, x5, eq msr cnthctl_el2, x2 /* Set the counter offset to a known value */ diff --git a/sys/arm64/include/hypervisor.h b/sys/arm64/include/hypervisor.h index ff6aff00e226..0ed21bf311c7 100644 --- a/sys/arm64/include/hypervisor.h +++ b/sys/arm64/include/hypervisor.h @@ -37,10 +37,15 @@ /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */ #define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */ +/* Valid if HCR_EL2.E2H == 0 */ +#define CNTHCTL_EL1PCTEN (1 << 0) /* Allow physical counter access */ +#define CNTHCTL_EL1PCEN (1 << 1) /* Allow physical timer access */ +/* Valid if HCR_EL2.E2H == 1 */ +#define CNTHCTL_E2H_EL1PCTEN (1 << 10) /* Allow physical counter access */ +#define CNTHCTL_E2H_EL1PTEN (1 << 11) /* Allow physical timer access */ +/* Unconditionally valid */ #define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */ #define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */ -#define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */ -#define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/ /* CPTR_EL2 - Architecture feature trap register */ #define CPTR_RES0 0x7fefc800
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