Date: Fri, 5 Jan 2018 11:17:52 -0800 From: Cy Schubert <Cy.Schubert@cschubert.com> To: Eric McCorkle <eric@metricspace.net>, "freebsd-security@freebsd.org" <freebsd-security@freebsd.org> Subject: RE: Intel hardware bug Message-ID: <20180105191747.EC625365@spqr.komquats.com>
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SPARC definitely does out of order execution. --- Sent using a tiny phone keyboard. Apologies for any typos and autocorrect. Also, this old phone only supports top post. Apologies. Cy Schubert <Cy.Schubert@cschubert.com> or <cy@freebsd.org> The need of the many outweighs the greed of the few. --- -----Original Message----- From: Eric McCorkle Sent: 05/01/2018 10:45 To: freebsd-security@freebsd.org Subject: Re: Intel hardware bug On 01/05/2018 11:40, Nathan Whitehorn wrote: > POWER has the same thing. It's actually stronger separation, since user > processes don't share addresses either -- all processes, including the > kernel, have windowed access to an 80-bit address space, so no process > can even describe an address in another process's address space. There > are ways, of course, in which IBM could have messed up the > implementation, so the fact that it *should* be secure does not mean it > *is*. That's interesting, as it conflicts with Red Hat's vulnerability disclosure. It that because the silicon is buggy, or because Linux somehow ends up being vulnerable when it need not be? >=20 > SPARC avoids the issue because almost all implementations are in-order. Definitely not true of the post-Oracle models. I saw a tech talk on the core once. _______________________________________________ freebsd-security@freebsd.org mailing list https://lists.freebsd.org/mailman/listinfo/freebsd-security To unsubscribe, send any mail to "freebsd-security-unsubscribe@freebsd.org"
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