Date: 17 Feb 2003 16:32:41 +0000 From: Doug Rabson <dfr@nlsystems.com> To: Marcel Moolenaar <marcel@xcllnt.net> Cc: Eric Anholt <eta@lclark.edu>, src-committers@FreeBSD.org, cvs-src@FreeBSD.org, cvs-all@FreeBSD.org Subject: Re: cvs commit: src/sys/modules Makefile Message-ID: <1045499561.1554.7.camel@builder02.qubesoft.com> In-Reply-To: <20030214061708.GA2109@athlon.pn.xcllnt.net> References: <20030213223058.769DA2A8C1@canning.wemm.org> <1045185451.11981.17.camel@leguin> <20030214023218.GA1573@athlon.pn.xcllnt.net> <1045194133.11981.87.camel@leguin> <20030214043028.GA1797@athlon.pn.xcllnt.net> <1045200753.84507.54.camel@leguin> <20030214061708.GA2109@athlon.pn.xcllnt.net>
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On Fri, 2003-02-14 at 06:17, Marcel Moolenaar wrote: > On Thu, Feb 13, 2003 at 09:32:33PM -0800, Eric Anholt wrote: > > > > > > In that case, we'd better make sure there's cache coherency. Do we > > > actually have the code structured in a way that allows having the > > > flushing chipset dependent (not to mention dependent on the address)? > > > > No, currently all the cache flushes (four in agp.c, three in i810 and > > amd code) are unconditional agp_flush_cache calls after modifying the > > gatt entries. They aren't tied to a specific memory range, but could be > > pretty easily, if not the most efficiently, by pushing some of them into > > the (un)bind_pages. There's probably a better way. > > I wonder: do we actually need to flush at all? GART updates are PCI/AGP > writes and should be coherent, right? > Isn't updating the SGM (system graphics memory) itself that needs > cache flushes to make sure the AGP device gets the right data? When I did the original intel agp driver, it was clear from testing that the chipset didn't see changes to the GATT unless the cache was explicitly flushed. I don't know about other chipsets. To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe cvs-src" in the body of the message
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