Skip site navigation (1)Skip section navigation (2) 
Date:      Sat, 9 Feb 2019 12:01:10 +0000 (UTC)
From:      Dimitry Andric <dim@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org
Subject:   svn commit: r343935 - in stable: 11/contrib/llvm/lib/CodeGen/SelectionDAG 12/contrib/llvm/lib/CodeGen/SelectionDAG
Message-ID:  <201902091201.x19C1Alp098374@repo.freebsd.org>
next in thread | raw e-mail | index | archive | help 
Author: dim
Date: Sat Feb  9 12:01:10 2019
New Revision: 343935
URL: https://svnweb.freebsd.org/changeset/base/343935

Log:
  MFC r342592:
  
  Pull in r342397 from upstream llvm trunk (by Amara Emerson):
  
    Revert "Revert r342183 "[DAGCombine] Fix crash when store merging
    created an extract_subvector with invalid index.""
  
    Fixed the assertion failure.
  
    Differential Revision: https://reviews.llvm.org/D51831
  
  This fixes 'Assertion failed: ((VT.getVectorNumElements() +
  N2C->getZExtValue() <= N1.getValueType().getVectorNumElements()) &&
  "Extract subvector overflow!"), function getNode' when building the
  multimedia/aom port (with AVX2 enabled).
  
  Reported by:	jbeich
  PR:		234480

Modified:
  stable/12/contrib/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Directory Properties:
  stable/12/   (props changed)

Changes in other areas also in this revision:
Modified:
  stable/11/contrib/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Directory Properties:
  stable/11/   (props changed)

Modified: stable/12/contrib/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
==============================================================================
--- stable/12/contrib/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Sat Feb  9 11:58:40 2019	(r343934)
+++ stable/12/contrib/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Sat Feb  9 12:01:10 2019	(r343935)
@@ -12851,17 +12851,24 @@ bool DAGCombiner::MergeStoresOfConstantsOrVecElts(
              Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) {
           SDValue Vec = Val.getOperand(0);
           EVT MemVTScalarTy = MemVT.getScalarType();
+          SDValue Idx = Val.getOperand(1);
           // We may need to add a bitcast here to get types to line up.
           if (MemVTScalarTy != Vec.getValueType()) {
             unsigned Elts = Vec.getValueType().getSizeInBits() /
                             MemVTScalarTy.getSizeInBits();
+            if (Val.getValueType().isVector() && MemVT.isVector()) {
+              unsigned IdxC = cast<ConstantSDNode>(Idx)->getZExtValue();
+              unsigned NewIdx =
+                  ((uint64_t)IdxC * MemVT.getVectorNumElements()) / Elts;
+              Idx = DAG.getConstant(NewIdx, SDLoc(Val), Idx.getValueType());
+            }
             EVT NewVecTy =
                 EVT::getVectorVT(*DAG.getContext(), MemVTScalarTy, Elts);
             Vec = DAG.getBitcast(NewVecTy, Vec);
           }
           auto OpC = (MemVT.isVector()) ? ISD::EXTRACT_SUBVECTOR
                                         : ISD::EXTRACT_VECTOR_ELT;
-          Val = DAG.getNode(OpC, SDLoc(Val), MemVT, Vec, Val.getOperand(1));
+          Val = DAG.getNode(OpC, SDLoc(Val), MemVT, Vec, Idx);
         }
         Ops.push_back(Val);
       }

Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201902091201.x19C1Alp098374>