Date: Wed, 8 Apr 2015 00:35:13 +0000 (UTC) From: Navdeep Parhar <np@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r281244 - in stable/10/sys/dev/cxgbe: . tom Message-ID: <201504080035.t380ZD0r054878@svn.freebsd.org>
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Author: np Date: Wed Apr 8 00:35:12 2015 New Revision: 281244 URL: https://svnweb.freebsd.org/changeset/base/281244 Log: MFC r276597: cxgbe/tom: do not engage the TOE's payload chopper for payload < 2 MSS or for 10Gbps ports. Modified: stable/10/sys/dev/cxgbe/offload.h stable/10/sys/dev/cxgbe/t4_main.c stable/10/sys/dev/cxgbe/tom/t4_cpl_io.c Directory Properties: stable/10/ (props changed) Modified: stable/10/sys/dev/cxgbe/offload.h ============================================================================== --- stable/10/sys/dev/cxgbe/offload.h Wed Apr 8 00:32:39 2015 (r281243) +++ stable/10/sys/dev/cxgbe/offload.h Wed Apr 8 00:35:12 2015 (r281244) @@ -147,6 +147,7 @@ struct tom_tunables { int indsz; int ddp_thres; int rx_coalesce; + int tx_align; }; int t4_register_uld(struct uld_info *); Modified: stable/10/sys/dev/cxgbe/t4_main.c ============================================================================== --- stable/10/sys/dev/cxgbe/t4_main.c Wed Apr 8 00:32:39 2015 (r281243) +++ stable/10/sys/dev/cxgbe/t4_main.c Wed Apr 8 00:35:12 2015 (r281244) @@ -4689,6 +4689,10 @@ t4_sysctls(struct adapter *sc) sc->tt.rx_coalesce = 1; SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); + + sc->tt.tx_align = 1; + SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", + CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); } #endif Modified: stable/10/sys/dev/cxgbe/tom/t4_cpl_io.c ============================================================================== --- stable/10/sys/dev/cxgbe/tom/t4_cpl_io.c Wed Apr 8 00:32:39 2015 (r281243) +++ stable/10/sys/dev/cxgbe/tom/t4_cpl_io.c Wed Apr 8 00:35:12 2015 (r281244) @@ -491,7 +491,7 @@ max_dsgl_nsegs(int tx_credits) static inline void write_tx_wr(void *dst, struct toepcb *toep, unsigned int immdlen, - unsigned int plen, uint8_t credits, int shove, int ulp_mode) + unsigned int plen, uint8_t credits, int shove, int ulp_mode, int txalign) { struct fw_ofld_tx_data_wr *txwr = dst; unsigned int wr_ulp_mode; @@ -513,6 +513,19 @@ write_tx_wr(void *dst, struct toepcb *to V_FW_OFLD_TX_DATA_WR_URGENT(0) | /* XXX */ V_FW_OFLD_TX_DATA_WR_SHOVE(shove)); txwr->plen = htobe32(plen); + + if (txalign > 0) { + struct tcpcb *tp = intotcpcb(toep->inp); + + if (plen < 2 * tp->t_maxseg || is_10G_port(toep->port)) + txwr->lsodisable_to_proxy |= + htobe32(F_FW_OFLD_TX_DATA_WR_LSODISABLE); + else + txwr->lsodisable_to_proxy |= + htobe32(F_FW_OFLD_TX_DATA_WR_ALIGNPLD | + (tp->t_flags & TF_NODELAY ? 0 : + F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)); + } } /* @@ -716,7 +729,8 @@ t4_push_frames(struct adapter *sc, struc } txwr = wrtod(wr); credits = howmany(wr->wr_len, 16); - write_tx_wr(txwr, toep, plen, plen, credits, shove, 0); + write_tx_wr(txwr, toep, plen, plen, credits, shove, 0, + sc->tt.tx_align); m_copydata(sndptr, 0, plen, (void *)(txwr + 1)); nsegs = 0; } else { @@ -734,7 +748,8 @@ t4_push_frames(struct adapter *sc, struc } txwr = wrtod(wr); credits = howmany(wr_len, 16); - write_tx_wr(txwr, toep, 0, plen, credits, shove, 0); + write_tx_wr(txwr, toep, 0, plen, credits, shove, 0, + sc->tt.tx_align); write_tx_sgl(txwr + 1, sndptr, m, nsegs, max_nsegs_1mbuf); if (wr_len & 0xf) { @@ -890,7 +905,7 @@ t4_ulp_push_frames(struct adapter *sc, s txwr = wrtod(wr); credits = howmany(wr->wr_len, 16); write_tx_wr(txwr, toep, plen, ulp_len, credits, shove, - ulp_mode); + ulp_mode, 0); m_copydata(sndptr, 0, plen, (void *)(txwr + 1)); } else { int wr_len; @@ -907,7 +922,7 @@ t4_ulp_push_frames(struct adapter *sc, s txwr = wrtod(wr); credits = howmany(wr_len, 16); write_tx_wr(txwr, toep, 0, ulp_len, credits, shove, - ulp_mode); + ulp_mode, 0); write_tx_sgl(txwr + 1, sndptr, m, nsegs, max_nsegs_1mbuf); if (wr_len & 0xf) {
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