Date: Sun, 28 Jun 2020 17:49:42 +0000 (UTC) From: Mitchell Horne <mhorne@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r362731 - stable/12/share/man/man7 Message-ID: <202006281749.05SHngdT099651@repo.freebsd.org>
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Author: mhorne Date: Sun Jun 28 17:49:41 2020 New Revision: 362731 URL: https://svnweb.freebsd.org/changeset/base/362731 Log: MFC r362546: arch(7): small corrections for RISC-V Modified: stable/12/share/man/man7/arch.7 Directory Properties: stable/12/ (props changed) Modified: stable/12/share/man/man7/arch.7 ============================================================================== --- stable/12/share/man/man7/arch.7 Sun Jun 28 17:47:41 2020 (r362730) +++ stable/12/share/man/man7/arch.7 Sun Jun 28 17:49:41 2020 (r362731) @@ -26,7 +26,7 @@ .\" .\" $FreeBSD$ .\" -.Dd January 8, 2020 +.Dd June 23, 2020 .Dt ARCH 7 .Os .Sh NAME @@ -258,8 +258,8 @@ is 8 bytes on all supported architectures except i386. .It powerpc Ta 4K .It powerpcspe Ta 4K .It powerpc64 Ta 4K -.It riscv64 Ta 4K -.It riscv64sf Ta 4K +.It riscv64 Ta 4K, 2M, 1G +.It riscv64sf Ta 4K, 2M, 1G .It sparc64 Ta 8K .El .Ss Floating Point @@ -283,8 +283,8 @@ is 8 bytes on all supported architectures except i386. .It powerpc Ta hard Ta hard, double precision .It powerpcspe Ta hard Ta hard, double precision .It powerpc64 Ta hard Ta hard, double precision -.It riscv64 Ta hard Ta hard, double precision -.It riscv64sf Ta soft Ta soft, double precision +.It riscv64 Ta hard Ta hard, quad precision +.It riscv64sf Ta soft Ta soft, quad precision .It sparc64 Ta hard Ta hard, quad precision .El .Pp @@ -378,7 +378,7 @@ Architecture-specific macros: .It powerpcspe Ta Dv __powerpc__, Dv __SPE__ .It powerpc64 Ta Dv __powerpc__, Dv __powerpc64__ .It riscv64 Ta Dv __riscv, Dv __riscv_xlen == 64 -.It riscv64sf Ta Dv __riscv, Dv __riscv_xlen == 64 +.It riscv64sf Ta Dv __riscv, Dv __riscv_xlen == 64, Dv __riscv_float_abi_soft .It sparc64 Ta Dv __sparc64__ .El .Pp
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