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Date:      Sat, 10 Mar 2001 22:34:18 -0800 (PST)
From:      "Justin T. Gibbs" <gibbs@FreeBSD.org>
To:        cvs-committers@FreeBSD.org, cvs-all@FreeBSD.org
Subject:   cvs commit: src/sys/dev/aic7xxx ahc_eisa.c ahc_pci.c aic7770.c aic7xxx.c aic7xxx.h aic7xxx.reg aic7xxx.seq aic7xxx_93cx6.c aic7xxx_freebsd.c aic7xxx_freebsd.h aic7xxx_inline.h aic7xxx_pci.c
Message-ID:  <200103110634.f2B6YLL53767@freefall.freebsd.org>

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gibbs       2001/03/10 22:34:18 PST

  Modified files:
    sys/dev/aic7xxx      ahc_eisa.c ahc_pci.c aic7770.c aic7xxx.c 
                         aic7xxx.h aic7xxx.reg aic7xxx.seq 
                         aic7xxx_93cx6.c aic7xxx_freebsd.c 
                         aic7xxx_freebsd.h aic7xxx_inline.h 
                         aic7xxx_pci.c 
  Log:
  This is an MFC candidate.
  
  ahc_eisa.c:
  	Change aic7770_map_int to take an additional irq parameter.
  	Although we can get the irq from the eisa dev under FreeBSD,
  	we can't do this under linux, so the OSM interface must supply
  	this.
  
  ahc_pci.c:
  	Move ahc_power_state_change() to the OSM.  This allows us to
  	use a platform supplied function that does the same thing.
  	-current will move to the FreeBSD native API in the near
  	future.
  
  aic7770.c:
  	Sync up with core changes to support Linux EISA.
  
  	We now store a 2 bit primary channel number rather
  	than a bit flag that only allows b to be the primary
  	channel.   Adjust for this change.
  
  aic7xxx.c:
  	Namespace and staticization cleanup.  All exported symbols
  	use an "ahc_" prefix to avoid collisions with other modules.
  
  	Correct a logic bug that prevented us from dropping
  	ATN during some exceptional conditions during message
  	processing.
  
  	Take advantage of a new flag managed by the sequencer
  	that indicates if an SCB fetch is in progress.  If so,
  	the currently selected SCB needs to be returned to the
  	free list to prevent an SCB leak.  This leak is a rarity
  	and would only occur if a bus reset or timeout resulting
  	in a bus reset occurred in the middle of an SCB fetch.
  
  	Don't attempt to perform ULTRA transfers on ultra capable
  	adapters missing the external precision resistor required
  	for ultra speeds.  I've never encountered an adapter
  	configured this way, but better safe than sorry.
  
          Handle the case of 5MHz user sync rate set as "0" instead of 0x1c
          in scratch ram.
  
          If we lookup a period of 0 in our table (async), clear the scsi offset.
  
  aic7xxx.h:
  	Adjust for the primary channel being represented as
  	a 2 bit integer in the flags member of the ahc softc.
  
  	Cleanup the flags definitions so that comment blocks are
  	not cramped.
  
  	Update seeprom definitions to correctly reflect the fact
  	that the primary channel is represented as a 2 bit integer.
  
  	Add AHC_ULTRA_DIASABLED softc flag to denote controllers
  	missing the external precision resistor.
  
  aic7xxx.reg:
  	Add DFCACHETH to the definition of DFSTATUS for completness sake.
  
  	Add SEQ_FLAGS2 which currently only contains the SCB_DMA
  	(SCB DMA in progress) flag.
  
  aic7xxx.seq:
  	Correct a problem when one lun has a disconnected untagged
  	transaction and another lun has disconnected tagged transactions.
  	Just because an entry is found in the untagged table doesn't
  	mean that it will match.  If the match on the lun fails, cleanup
  	the SCB (return it to the disconnected list or free it), and snoop
  	for a tag message.  Before this change, we reported an unsolicited
  	reselection.  This bug was introduced about a month ago during an
  	overly aggressive optimization pass on the reselection code.
  
  	When cleaning up an SCB, we can't just blindly free the SCB.  In
  	the paging case, if the SCB came off of the disconnected list, its
  	state may never have been updated in host memory.  So, check the
  	disconnected bit in SCB_CONTROL and return the SCB to the disconnected
  	list if appropriate.
  
  	Manage the SCB_DMA flag of SEQ_FLAGS2.
  
  	More carefully shutdown the S/G dma engine in all cases by using
  	a subroutine.  Supposedly not doing this can cause an arbiter hang
  	on some ULTRA2 chips.
  
  	Formatting cleanup.
  
  	On some chips, at least the aic7856, the transition from
  	MREQPEND to HDONE can take a full 4 clock cycles.  Test
  	HDONE one more time to avoid this race.  We only want our
  	FIFO hung recovery code to execute when the engine is
  	really hung.
  
  aic7xxx_93cx6.c:
  	Sync perforce ids.
  
  aic7xxx_freebsd.c:
  	Adjust for the primary channel being a 2 bit integer
  	rather than a flag for 'B' channel being the primary.
  
  	Namespace cleanup.
  
  	Unpause the sequencer in one error recovery path that
  	neglected to do so.  This could have caused us to perform
  	a bus reset when a recovery message might have otherwise been
  	successful.
  
  aic7xxx_freebsd.h:
  	Use AHC_PCI_CONFIG for controlling compilation of PCI
  	support consistently throughout the driver.
  
  	Move ahc_power_state_change() to OSM.
  
  aic7xxx_inline.h
  	Namespace cleanup.
  
  	Adjust our interrupt handler so it will work in the edge
  	interrupt case.  We must process all interrupt sources
  	when the interrupt fires or risk not ever getting an
  	interrupt again.  This involves marking the fact
  	that we are relying on an edge interrupt in ahc->flags
  	and checking for this condition in addition to the
  	AHC_ALL_INTERRUPTS flag.  This fixes hangs on the
  	284X and any other aic7770 installation where level
  	interrupts are not available.
  
  aic7xxx_pci.c:
  	Move the powerstate manipulation code into the OSM.  Several
  	OSes now provide this functionality natively.
  
  	Take another shot at using the data stored in scratch ram
  	if the SCB2 signature is correct and no SEEPROM data is
  	available.  In the past this failed if external SCB ram
  	was configured because the memory port was locked.  We
  	now release the memory port prior to testing the values
  	in SCB2 and re-acquire it prior to doing termination control.
  
  	Adjust for new 2 bit primary channel setting.
  
  	Trust the STPWLEVEL setting on v 3.X BIOSes too.
  
  	Configure any 785X ID in the same fashion and assume
  	that any device with a rev id of 1 or higher has the
  	PCI 2.1 retry bug.
  
  Revision  Changes    Path
  1.21      +2 -2      src/sys/dev/aic7xxx/ahc_eisa.c
  1.41      +36 -1     src/sys/dev/aic7xxx/ahc_pci.c
  1.4       +26 -5     src/sys/dev/aic7xxx/aic7770.c
  1.71      +119 -65   src/sys/dev/aic7xxx/aic7xxx.c
  1.37      +40 -48    src/sys/dev/aic7xxx/aic7xxx.h
  1.35      +7 -2      src/sys/dev/aic7xxx/aic7xxx.reg
  1.113     +101 -70   src/sys/dev/aic7xxx/aic7xxx.seq
  1.13      +2 -2      src/sys/dev/aic7xxx/aic7xxx_93cx6.c
  1.23      +12 -15    src/sys/dev/aic7xxx/aic7xxx_freebsd.c
  1.8       +15 -4     src/sys/dev/aic7xxx/aic7xxx_freebsd.h
  1.14      +26 -17    src/sys/dev/aic7xxx/aic7xxx_inline.h
  1.13      +129 -160  src/sys/dev/aic7xxx/aic7xxx_pci.c


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