Date: Wed, 14 Dec 2005 18:22:12 GMT From: Warner Losh <imp@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 88182 for review Message-ID: <200512141822.jBEIMCK2082404@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=88182 Change 88182 by imp@imp_Speedy on 2005/12/14 18:21:57 Slight reorg of the names of the serial devices. The USARTs are used in a variety of AT91 cpus. Hope I got them basically right. Moved USART defines from at91rm92reg.h to at92usartreg.h Affected files ... .. //depot/projects/arm/src/sys/arm/at91/at91rm92reg.h#7 edit .. //depot/projects/arm/src/sys/arm/at91/at91usartreg.h#1 add .. //depot/projects/arm/src/sys/arm/at91/files.at91rm92#3 edit .. //depot/projects/arm/src/sys/arm/at91/uart_bus_at91rm92usart.c#4 delete .. //depot/projects/arm/src/sys/arm/at91/uart_bus_at91usart.c#1 add .. //depot/projects/arm/src/sys/arm/at91/uart_cpu_at91rm9200usart.c#1 add .. //depot/projects/arm/src/sys/arm/at91/uart_cpu_at91rm92usart.c#6 delete .. //depot/projects/arm/src/sys/arm/at91/uart_dev_at91rm92usart.c#4 delete .. //depot/projects/arm/src/sys/arm/at91/uart_dev_at91usart.c#1 branch Differences ... ==== //depot/projects/arm/src/sys/arm/at91/at91rm92reg.h#7 (text+ko) ==== @@ -54,66 +54,6 @@ #define AT91RM92_USART3_PDC 0xffcc100 #define AT91RM92_USART_SIZE 0x4000 -#define USART_CR 0x00 /* Control register */ -#define USART_CR_RSTRX (1 << 2) /* Reset Receiver */ -#define USART_CR_RSTTX (1 << 3) /* Reset Transmitter */ -#define USART_CR_RXEN (1 << 4) /* Receiver Enable */ -#define USART_CR_RXDIS (1 << 5) /* Receiver Disable */ -#define USART_CR_TXEN (1 << 6) /* Transmitter Enable */ -#define USART_CR_TXDIS (1 << 7) /* Transmitter Disable */ -#define USART_CR_RSTSTA (1 << 8) /* Reset Status Bits */ -#define USART_CR_STTBRK (1 << 9) /* Start Break */ -#define USART_CR_STPBRK (1 << 10) /* Stop Break */ -#define USART_CR_STTTO (1 << 11) /* Start Time-out */ -#define USART_CR_SENDA (1 << 12) /* Send Address */ -#define USART_CR_RSTIT (1 << 13) /* Reset Iterations */ -#define USART_CR_RSTNACK (1 << 14) /* Reset Non Acknowledge */ -#define USART_CR_RETTO (1 << 15) /* Rearm Time-out */ -#define USART_CR_DTREN (1 << 16) /* Data Terminal ready Enable */ -#define USART_CR_DTRDIS (1 << 17) /* Data Terminal ready Disable */ -#define USART_CR_RTSEN (1 << 18) /* Request to Send enable */ -#define USART_CR_RTSDIS (1 << 19) /* Request to Send Disable */ - -#define USART_MR 0x04 /* Mode register */ -#define USART_IER 0x08 /* Interrupt enable register */ -#define USART_IDR 0x0c /* Interrupt disable register */ -#define USART_IMR 0x10 /* Interrupt mask register */ -#define USART_CSR 0x14 /* Channel status register */ - -#define USART_CSR_RXRDY (1 << 0) /* Receiver ready */ -#define USART_CSR_TXRDY (1 << 1) /* Transmitter ready */ - -#define USART_RHR 0x18 /* Receiver holding register */ -#define USART_THR 0x1c /* Transmitter holding register */ -#define USART_BRGR 0x20 /* Baud rate generator register */ -#define USART_RTOR 0x24 /* Receiver time-out register */ -#define USART_TTR 0x28 /* Transmitter timeguard register */ -/* 0x2c to 0x3c reserved */ -#define USART_FDRR 0x40 /* FI DI ratio register */ -#define USART_NER 0x44 /* Number of errors register */ -/* 0x48 reserved */ -#define USART_IFR 0x48 /* IrDA filter register */ - - -#define UART_RXRDY (0x1 << 0) /* RXRDY Interrupt */ -#define UART_TXRDY (0x1 << 1) /* TXRDY Interrupt */ -#define UART_RXBRK (0x1 << 2) /* Break Received/End of Break */ -#define UART_ENDRX (0x1 << 3) /* End of Receive Transfer Interrupt */ -#define UART_ENDTX (0x1 << 4) /* End of Transmit Interrupt */ -#define UART_OVRE (0x1 << 5) /* Overrun Interrupt */ -#define UART_FRAME (0x1 << 6) /* Framing Error Interrupt */ -#define UART_PARE (0x1 << 7) /* Parity Error Interrupt */ -#define UART_TIMEOUT ( 0x1 << 8) /* (USART) Receiver Time-out */ -#define UART_TXEMPTY ( 0x1 << 9) /* (USART) TXEMPTY Interrupt */ -#define UART_ITERATION ( 0x1 << 10) /* (USART) Max number of Repetitions Reached */ -#define UART_TXBUFE ( 0x1 << 11) /* (USART) TXBUFE Interrupt */ -#define UART_RXBUFF ( 0x1 << 12) /* (USART) RXBUFF Interrupt */ -#define UART_NACK ( 0x1 << 13) /* (USART) Non Acknowledge */ -#define UART_RIIC ( 0x1 << 16) /* (USART) Ring INdicator Input Change Flag */ -#define AT91RM92_US_DSRIC ( 0x1 << 17) /* (USART) Data Set Ready Input Change Flag */ -#define AT91RM92_US_DCDIC ( 0x1 << 18) /* (USART) Data Carrier Flag */ -#define AT91RM92_US_CTSIC ( 0x1 << 19) /* (USART) Clear To Send Input Change Flag */ - /* System Registers */ #define AT91RM92_SYS_BASE 0xffff000 @@ -140,28 +80,11 @@ /* DBGU */ -#define DBGU_CR (0x200) /* Control register */ -#define DBGU_MR (0x200 + 4) /* Mode register */ -#define DBGU_IER (0x200 + 8) /* Interrupt Enable Register */ -#define DBGU_IDR (0x200 + 12) /* Interrupt Disable Register */ -#define DBGU_IMR (0x200 + 16) /* Interrupt Mask Register */ -#define DBGU_CSR (0x200 + 20) /* Channel Status Register */ -#define DBGU_RHR (0x200 + 24) /* Receiver Holding Register */ -#define DBGU_THR (0x200 + 28) /* Transmitter Holding Register */ -#define DBGU_BRGR (0x200 + 32) /* Baud Rate Generator Register */ +#define DBGU 0x200 +#define DBGU_SIZE 0x200 #define DBGU_C1R (0x200 + 64) /* Chip ID1 Register */ #define DBGU_C2R (0x200 + 68) /* Chip ID2 Register */ #define DBGU_FNTR (0x200 + 72) /* Force NTRST Register */ -#define DBGU_RPR (0x200 + 256) /* Receive Pointer Register */ -#define DBGU_RCR (0x200 + 260) /* Receive Counter Register */ -#define DBGU_TPR (0x200 + 264) /* Transmit Pointer Register */ -#define DBGU_TCR (0x200 + 268) /* Transmit Counter Register */ -#define DBGU_RNPR (0x200 + 272) /* Receive Next Pointer Register */ -#define DBGU_RNCR (0x200 + 276) /* Receive Next Counter Register */ -#define DBGU_TNPR (0x200 + 280) /* Transmit Next Pointer Register */ -#define DBGU_TNCR (0x200 + 284) /* Transmit Next Counter Register */ -#define DBGU_PTCR (0x200 + 288) /* PDC Transfer Control Register */ -#define DBGU_PTSR (0x200 + 292) /* PDC Transfer Status Register */ #define PIOA_PER (0x400) /* PIO Enable Register */ #define PIOA_PDR (0x400 + 4) /* PIO Disable Register */ ==== //depot/projects/arm/src/sys/arm/at91/files.at91rm92#3 (text+ko) ==== @@ -3,6 +3,6 @@ arm/arm/irq_dispatch.S standard arm/at91/at91rm92.c standard arm/at91/at91rm92timer.c standard -arm/at91/uart_bus_at91rm92usart.c optional uart -arm/at91/uart_cpu_at91rm92usart.c optional uart -arm/at91/uart_dev_at91rm92usart.c optional uart +arm/at91/uart_bus_at91usart.c optional uart +arm/at91/uart_cpu_at91rm9200usart.c optional uart +arm/at91/uart_dev_at91usart.c optional uart
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