Date: Wed, 10 Jun 2026 14:08:18 +0000 From: Justin Hibbits <jhibbits@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: 4bdcff554368 - main - powerpc/booke: Add watchdog driver Message-ID: <6a296fd2.1fbdd.44ea01c6@gitrepo.freebsd.org>
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The branch main has been updated by jhibbits: URL: https://cgit.FreeBSD.org/src/commit/?id=4bdcff55436859420e090afb0e6932bab794baa4 commit 4bdcff55436859420e090afb0e6932bab794baa4 Author: Justin Hibbits <jhibbits@FreeBSD.org> AuthorDate: 2026-06-10 03:09:10 +0000 Commit: Justin Hibbits <jhibbits@FreeBSD.org> CommitDate: 2026-06-10 14:04:41 +0000 powerpc/booke: Add watchdog driver The Book-E watchdog is effectively a state machine based around an AND mask of the timebase register. A single bit (0-63) is watched in the timebase register, and when it transitions (by counting *or* by programmatically setting) an exception is triggered. The first exception triggers a core interrupt. The second is programmable. In our case, we panic on the first and reset on second. --- sys/powerpc/booke/machdep_e500.c | 71 ++++++++++++++++++++++++++++++++++++++++ sys/powerpc/include/spr.h | 3 ++ 2 files changed, 74 insertions(+) diff --git a/sys/powerpc/booke/machdep_e500.c b/sys/powerpc/booke/machdep_e500.c index d56209c12faa..2f39a66aac6d 100644 --- a/sys/powerpc/booke/machdep_e500.c +++ b/sys/powerpc/booke/machdep_e500.c @@ -30,8 +30,11 @@ #include <sys/types.h> #include <sys/param.h> +#include <sys/kernel.h> +#include <sys/eventhandler.h> #include <sys/proc.h> #include <sys/reboot.h> +#include <sys/smp.h> #include <vm/vm.h> #include <vm/pmap.h> @@ -136,3 +139,71 @@ cpu_machine_check(struct thread *td, struct trapframe *frame, int *ucode) *ucode = BUS_OBJERR; return (SIGBUS); } + +/* + * Book-E watchdog timer is a simple check of a single bit in the timebase + * register. When that bit rolls over from 0 to 1 the state machine activates. + * In our case, we want it to trigger an interrupt to the core first, then + * reboot on the second interrupt. + * + * With all PowerPC numbering, 0 is the MSB, and 63 is LSB. + */ +/* Arg is the timebase bit number 1-based (flsll result) */ +static void +booke_watchdog_cpu(void *arg) +{ + uint32_t tcr; + int bitno = (uintptr_t)arg; + + /* First pet the watchdog */ + mtspr(SPR_TSR, TSR_ENW | TSR_WIS); + + tcr = mfspr(SPR_TCR); + tcr &= ~(TCR_WP_MASK | TCR_WPEXT_MASK); + tcr |= TCR_MAKE_WP(bitno); + + tcr |= TCR_WRC_CHIP | TCR_WIE; + + mtspr(SPR_TCR, tcr); +} + +static void +booke_watchdog_fn(void *priv, sbintime_t sbt, sbintime_t *esbt, int *err) +{ + struct cpuref cpuref; + uintptr_t tb_bit; + uint64_t freq, tb, ticks; + + /* Once enabled it cannot be disabled */ + if (sbt == 0) { + *err = EOPNOTSUPP; + return; + } + cpuref.cr_hwref = 0; + cpuref.cr_cpuid = 0; + freq = platform_timebase_freq(&cpuref); + ticks = 1000000000 / freq; /* Ticks/s -> ns/tick */ + ticks = sbttons(sbt) / ticks; + + /* + * To get the next rollover bit add the current timbase to the tick + * count, using only a mask of the current timebase matching the tick + * size. This will give us the next rollover bit *beyond* the timeout. + */ + tb = mftb() & ((1 << flsll(ticks)) - 1); + tb += ticks; + + tb_bit = 64 - flsll(tb); + + smp_rendezvous(NULL, booke_watchdog_cpu, NULL, (void *)tb_bit); + *err = 0; +} + +static void +booke_watchdog_register(void *arg) +{ + printf("Registering booke watchdog timer\n"); + EVENTHANDLER_REGISTER(watchdog_sbt_list, booke_watchdog_fn, NULL, 0); +} + +SYSINIT(booke_watchdog, SI_SUB_LAST, SI_ORDER_ANY, booke_watchdog_register, NULL); diff --git a/sys/powerpc/include/spr.h b/sys/powerpc/include/spr.h index 5c6e9d67fcb4..afa1692bed75 100644 --- a/sys/powerpc/include/spr.h +++ b/sys/powerpc/include/spr.h @@ -549,6 +549,9 @@ #define TCR_FP_2_21 0x03000000 /* 2**21 clocks */ #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ #define TCR_ARE 0x00400000 /* Auto Reload Enable */ +#define TCR_WPEXT_MASK 0x003c0000 +#define TCR_FPEXT_MASK 0x0003c000 +#define TCR_MAKE_WP(c) (((c & 0x3) << 30) | (c & 0x3c) << 15) #define SPR_HID0 0x3f0 /* ..8 Hardware Implementation Register 0 */ #define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */home | help
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