Date: Sat, 11 Feb 2012 19:05:18 +0200 From: Andriy Gapon <avg@FreeBSD.org> To: Alexander Motin <mav@FreeBSD.org>, freebsd-hackers@FreeBSD.org Subject: Re: [RFT][patch] Scheduling for HTT and not only Message-ID: <4F369FCE.7080408@FreeBSD.org> In-Reply-To: <4F366E8F.9060207@FreeBSD.org> References: <4F2F7B7F.40508@FreeBSD.org> <4F366E8F.9060207@FreeBSD.org>
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on 11/02/2012 15:35 Andriy Gapon said the following: > It seems that on modern CPUs the caches are either inclusive or some smart "as > if inclusive" caches. As a result, if two cores have a shared cache at any > level, then it should be relatively cheap to move a thread from one core to the > other. E.g. if logical CPUs P0 and P1 have private L1 and L2 caches and a > shared L3 cache, then on modern processors it should be much cheaper to move a > thread from P0 to P1 than to some processor P2 that doesn't share the L3 cache Having read this paper http://www.cs.uwaterloo.ca/~brecht/courses/856/Possible-Readings/multicore/cache-performance-x86-2009.pdf I think that I have been too optimistic about the smartness of caches in some processors... -- Andriy Gapon
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