Date: Thu, 30 Apr 2026 00:18:11 +0000 From: Justin Hibbits <jhibbits@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: 605f53705d6d - main - powerpc/openpic: Increase the maximum number of IRQs allowed Message-ID: <69f29fc3.317a8.192fc00b@gitrepo.freebsd.org>
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The branch main has been updated by jhibbits: URL: https://cgit.FreeBSD.org/src/commit/?id=605f53705d6dc57ed391353cecf3ce84a4283740 commit 605f53705d6dc57ed391353cecf3ce84a4283740 Author: Justin Hibbits <jhibbits@FreeBSD.org> AuthorDate: 2026-04-30 00:13:11 +0000 Commit: Justin Hibbits <jhibbits@FreeBSD.org> CommitDate: 2026-04-30 00:13:48 +0000 powerpc/openpic: Increase the maximum number of IRQs allowed The Freescale MPIC supports up to 2048 IRQs, but since we only build an array of 768 interrupts in intr_machdep, clamp the max at 512. The most any Freescale PowerPC chip actually supports is 452 on the T4240, so 512 is sufficient. As part of this, increase the vector mask to the full openpic vector mask, and use this limit as the terminator for the dispatch loop, instead of a hard-coded 255. Differential Revision: https://reviews.freebsd.org/D56422 --- sys/powerpc/include/openpicreg.h | 2 +- sys/powerpc/include/openpicvar.h | 3 ++- sys/powerpc/powerpc/openpic.c | 10 ++++++++-- 3 files changed, 11 insertions(+), 4 deletions(-) diff --git a/sys/powerpc/include/openpicreg.h b/sys/powerpc/include/openpicreg.h index 16f0295469e2..03c259d115b5 100644 --- a/sys/powerpc/include/openpicreg.h +++ b/sys/powerpc/include/openpicreg.h @@ -112,7 +112,7 @@ #define OPENPIC_ACTIVITY 0x40000000 #define OPENPIC_PRIORITY_MASK 0x000f0000 #define OPENPIC_PRIORITY_SHIFT 16 -#define OPENPIC_VECTOR_MASK 0x000000ff +#define OPENPIC_VECTOR_MASK 0x0000ffff /* interrupt destination cpu */ #ifndef OPENPIC_IDEST diff --git a/sys/powerpc/include/openpicvar.h b/sys/powerpc/include/openpicvar.h index 12f01cb80406..4f086f809f08 100644 --- a/sys/powerpc/include/openpicvar.h +++ b/sys/powerpc/include/openpicvar.h @@ -32,7 +32,7 @@ #define OPENPIC_DEVSTR "OpenPIC Interrupt Controller" -#define OPENPIC_IRQMAX 256 /* h/w allows more */ +#define OPENPIC_IRQMAX 512 /* h/w allows more */ #define OPENPIC_QUIRK_SINGLE_BIND 1 /* Bind interrupts to only 1 CPU */ #define OPENPIC_QUIRK_HIDDEN_IRQS 2 /* May have IRQs beyond FRR[NIRQ] */ @@ -59,6 +59,7 @@ struct openpic_softc { u_int sc_nirq; int sc_psim; u_int sc_quirks; + uint32_t sc_vec_mask; /* Saved states. */ uint32_t sc_saved_config; diff --git a/sys/powerpc/powerpc/openpic.c b/sys/powerpc/powerpc/openpic.c index bdd59407e3d4..3cb4c544a91a 100644 --- a/sys/powerpc/powerpc/openpic.c +++ b/sys/powerpc/powerpc/openpic.c @@ -151,6 +151,12 @@ openpic_common_attach(device_t dev, uint32_t node) OPENPIC_FEATURE_LAST_CPU_SHIFT) + 1; sc->sc_nirq = ((x & OPENPIC_FEATURE_LAST_IRQ_MASK) >> OPENPIC_FEATURE_LAST_IRQ_SHIFT) + 1; + /* + * Generate the vector mask used for IACK. + * Some PICs may not support the full 11 bit vector width, so clamp the + * mask to only the next-power-of-2 from the max IRQ. + */ + sc->sc_vec_mask = (1 << fls(sc->sc_nirq)) - 1; /* * PSIM seems to report 1 too many IRQs and CPUs @@ -294,8 +300,8 @@ openpic_dispatch(device_t dev, struct trapframe *tf) while (1) { vector = openpic_read(sc, OPENPIC_PCPU_IACK(cpuid)); - vector &= OPENPIC_VECTOR_MASK; - if (vector == 255) + vector &= sc->sc_vec_mask; + if (vector == sc->sc_vec_mask) break; powerpc_dispatch_intr(vector, tf); }home | help
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