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Date:      Wed, 27 Aug 2014 21:05:39 -0700
From:      Bart Kus <me@bartk.us>
To:        freebsd-wireless@freebsd.org
Subject:   Re: FreeBSD TDMA: Legalizing 440MHz 802.11 modems
Message-ID:  <53FEAA93.1020505@bartk.us>
In-Reply-To: <53FEA94A.3080602@bartk.us>
References:  <53FE5CF4.1000901@bartk.us>	<CAJ-VmokUyrvE-2bgkHDE9sCGJv_3EEffqWVWySvYf=7ra4PfUA@mail.gmail.com>	<53FE6513.8040107@bartk.us>	<CAJ-VmomNCMy8%2BihYyFFSW1oTVKNQDaaQjXqDxYLxDWCLjb0dDg@mail.gmail.com>	<53FE6BDC.5030306@bartk.us> <CAJ-VmonTTPfpHzAF-L95EP4ZXChH1Gb4AKmkPYNC6YE3ymqQ0g@mail.gmail.com> <53FEA94A.3080602@bartk.us>

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Fixed original email with imgur URL since mailing list strips attachments.

--Bart


On 8/27/2014 9:00 PM, Bart Kus wrote:
> Well I'll be damned, looks like 5MHz mode on Mikrotik is just slower 
> signalling!  All 52-subcarriers are indeed there, although a little 
> hard to see:
>
> http://i.imgur.com/d50zApc.png
>
> If you count peaks left/right of center, you'll get 26.  2*26=52, so 
> that's every sub accounted for.
>
> Can you point me at your 5/10MHz docs?  And which analog filter you're 
> referring to?
>
> --Bart
>
>
>
>
> On 8/27/2014 4:47 PM, Adrian Chadd wrote:
>> On 27 August 2014 16:38, Bart Kus <me@bartk.us> wrote:
>>> I'm guessing the chip generates its own internal clocks from an 
>>> external
>>> reference.  Can that PLL be slowed down ahead of timers overflowing?
>>> Hopefully the PCI clock is generated independently.
>> Yeah, that's what you're slowing down - you program the PLL.
>>
>> The PCI clock is generated separately.
>>
>>> Also, I think Mikrotik implements narrower bands by dropping 
>>> subcarriers
>>> instead of slowing down their symbol rates.  I'll try to get a good 
>>> spectrum
>>> picture of their 5MHz mode tonight. Keeping the subcarrier symbol rates
>>> relatively higher might offset some analog droops, at the cost of 
>>> OFDM skirt
>>> sharpness.
>> Hey cool, if they're doing that then I should likely go digging for
>> the PHY documentation for the AR5414 and find out.
>>
>>> Also, a slight correction.  I think you meant the subs are 312.5kHz 
>>> wide,
>>> which would result in a 200kHz emission having 3.125kHz wide subs.  Or,
>>> perhaps more realistically, running at 1/128th the speed, 2.44140625kHz
>>> wide.  How can you not love a number like that? :)
>> Someone else can do better math, I'm busy doing non-wifi at the 
>> moment. :)
>>
>> But, it really is 20MHz / 64 carriers == each subcarrier width.
>>
>>> Does the project have a map of all these clocks + timers which might 
>>> need
>>> tweaking for spectrum reduction?  I know you can't cite original 
>>> Atheros
>>> docs, but perhaps there's been derivative documentation works created?
>> Not at the moment I'm afraid. I haven't really dug into that level of
>> detail. I documented what's needed for 5 and 10MHz modes.
>>
>> However - there's an analog filter that I don't know if it's
>> programmable or not. It's used for both transmit and receive
>> filtering. I know on these chips it can do 5/10/20/40 but I don't know
>> if it's an arbitrary width.
>>
>>
>> -a
>
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