Date: Sat, 18 Sep 2021 17:32:56 +0000 From: bugzilla-noreply@freebsd.org To: bugs@FreeBSD.org Subject: [Bug 258580] vte(4): restore MDC clock speed register value after MAC reset Message-ID: <bug-258580-227@https.bugs.freebsd.org/bugzilla/>
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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=3D258580 Bug ID: 258580 Summary: vte(4): restore MDC clock speed register value after MAC reset Product: Base System Version: CURRENT Hardware: i386 OS: Any Status: New Severity: Affects Some People Priority: --- Component: kern Assignee: bugs@FreeBSD.org Reporter: vezhlys@gmail.com Created attachment 227988 --> https://bugs.freebsd.org/bugzilla/attachment.cgi?id=3D227988&action= =3Dedit if_vte.c patch Hi, On some Vortex86 SoCs MDC speed control register needs to be restored to original value after MAC reset. This issue happens if MAC has non default VTE_MDCSC register value before reset, and it is erroneously set to default after, thus causing certain PHY registers fail to be read. Since PHY regist= ers determine link status, the link is never established (ifconfig media shows "none" value). Also, one obvious sign is incorrect (not RDC) oui value in dmesg. Initially, I found and fixed that in NetBSD, but it affects all BSDs and Li= nux. Patch is already applied on NetBSD (http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/dev/pci/if_vte.c.diff?r1=3D1.3= 1&r2=3D1.32) and Linux (https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git/commit/?id= =3De3f0cc1a945fcefec0c7c9d9dfd028a51daa1846). Sending exactly the same patch for FreeBSD. For more info and my debugging history can be found in http://gnats.netbsd.org/cgi-bin/query-pr-single.pl?number=3D53494 thread. I tested the patch on my affected Vortex86DX3 based system (link is established/oui is correct), and unaffected DX2, EX2 based machines on Free= BSD (the patch itself was tested by few more people in NetBSD/Linux too). --=20 You are receiving this mail because: You are the assignee for the bug.=
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