Date: Tue, 30 Jun 2009 12:35:47 +0000 (UTC) From: Stanislav Sedov <stas@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r195189 - in head: share/man/man4 sys/dev/cpuctl sys/sys usr.sbin/cpucontrol Message-ID: <200906301235.n5UCZlmE080805@svn.freebsd.org>
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Author: stas Date: Tue Jun 30 12:35:47 2009 New Revision: 195189 URL: http://svn.freebsd.org/changeset/base/195189 Log: - Add support to atomically set/clear individual bits of a MSR register via cpuctl(4) driver. Two new CPUCTL_MSRSBIT and CPUCTL_MSRCBIT ioctl(2) calls treat the data field of the argument struct passed as a mask and set/clear bits of the MSR register according to the mask value. - Allow user to perform atomic bitwise AND and OR operaions on MSR registers via cpucontrol(8) utility. Two new operations ("&=" and "|=") have been added. The first one applies bitwise AND operaion between the current contents of the MSR register and the mask, and the second performs bitwise OR. The argument can be optionally prefixed with "~" inversion operator. This allows one to mimic the "clear bit" behavior by using the command like this: cpucontrol -m 0x10&=~0x02 # clear the second bit of TSC MSR Inversion operator support in all modes (assignment, OR, AND). Approved by: re (kib) MFC after: 1 month Modified: head/share/man/man4/cpuctl.4 head/sys/dev/cpuctl/cpuctl.c head/sys/sys/cpuctl.h head/usr.sbin/cpucontrol/cpucontrol.8 head/usr.sbin/cpucontrol/cpucontrol.c Modified: head/share/man/man4/cpuctl.4 ============================================================================== --- head/share/man/man4/cpuctl.4 Tue Jun 30 11:16:32 2009 (r195188) +++ head/share/man/man4/cpuctl.4 Tue Jun 30 12:35:47 2009 (r195189) @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd May 31, 2008 +.Dd June 30, 2009 .Dt CPUCTL 4 .Os .Sh NAME @@ -81,6 +81,11 @@ typedef struct { uint64_t data; } cpuctl_msr_args_t; .Ed +.It Dv CPUCTL_MSRSBIT Fa cpuctl_msr_args_t *args +.It Dv CPUCTL_MSRCBIT Fa cpuctl_msr_args_t *args +Set/clear MSR bits according to the mask given in the +.Va data +field. .It Dv CPUCTL_CPUID Fa cpuctl_cpuid_args_t *args Retrieve CPUID information. Arguments are supplied in Modified: head/sys/dev/cpuctl/cpuctl.c ============================================================================== --- head/sys/dev/cpuctl/cpuctl.c Tue Jun 30 11:16:32 2009 (r195188) +++ head/sys/dev/cpuctl/cpuctl.c Tue Jun 30 12:35:47 2009 (r195189) @@ -158,6 +158,8 @@ cpuctl_ioctl(struct cdev *dev, u_long cm case CPUCTL_RDMSR: ret = cpuctl_do_msr(cpu, (cpuctl_msr_args_t *)data, cmd, td); break; + case CPUCTL_MSRSBIT: + case CPUCTL_MSRCBIT: case CPUCTL_WRMSR: ret = priv_check(td, PRIV_CPUCTL_WRMSR); if (ret != 0) @@ -211,6 +213,7 @@ cpuctl_do_cpuid(int cpu, cpuctl_cpuid_ar static int cpuctl_do_msr(int cpu, cpuctl_msr_args_t *data, u_long cmd, struct thread *td) { + uint64_t reg; int is_bound = 0; int oldcpu; int ret; @@ -230,9 +233,22 @@ cpuctl_do_msr(int cpu, cpuctl_msr_args_t if (cmd == CPUCTL_RDMSR) { data->data = 0; ret = rdmsr_safe(data->msr, &data->data); - } else { + } else if (cmd == CPUCTL_WRMSR) { ret = wrmsr_safe(data->msr, data->data); - } + } else if (cmd == CPUCTL_MSRSBIT) { + critical_enter(); + ret = rdmsr_safe(data->msr, ®); + if (ret == 0) + ret = wrmsr_safe(data->msr, reg | data->data); + critical_exit(); + } else if (cmd == CPUCTL_MSRCBIT) { + critical_enter(); + ret = rdmsr_safe(data->msr, ®); + if (ret == 0) + ret = wrmsr_safe(data->msr, reg & ~data->data); + critical_exit(); + } else + panic("[cpuctl,%d]: unknown operation requested: %lu", __LINE__, cmd); restore_cpu(oldcpu, is_bound, td); return (ret); } Modified: head/sys/sys/cpuctl.h ============================================================================== --- head/sys/sys/cpuctl.h Tue Jun 30 11:16:32 2009 (r195188) +++ head/sys/sys/cpuctl.h Tue Jun 30 12:35:47 2009 (r195189) @@ -48,5 +48,7 @@ typedef struct { #define CPUCTL_WRMSR _IOWR('c', 2, cpuctl_msr_args_t) #define CPUCTL_CPUID _IOWR('c', 3, cpuctl_cpuid_args_t) #define CPUCTL_UPDATE _IOWR('c', 4, cpuctl_update_args_t) +#define CPUCTL_MSRSBIT _IOWR('c', 5, cpuctl_msr_args_t) +#define CPUCTL_MSRCBIT _IOWR('c', 6, cpuctl_msr_args_t) #endif /* _CPUCTL_H_ */ Modified: head/usr.sbin/cpucontrol/cpucontrol.8 ============================================================================== --- head/usr.sbin/cpucontrol/cpucontrol.8 Tue Jun 30 11:16:32 2009 (r195188) +++ head/usr.sbin/cpucontrol/cpucontrol.8 Tue Jun 30 12:35:47 2009 (r195189) @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd August 4, 2008 +.Dd June 30, 2009 .Dt CPUCONTROL 8 .Os .Sh NAME @@ -35,7 +35,25 @@ device. .Sh SYNOPSIS .Nm .Op Fl vh -.Fl m Ar msr Ns Op = Ns Ar value +.Fl m Ar msr +.Bk +.Ar device +.Ek +.Nm +.Op Fl vh +.Fl m Ar msr Ns = Ns Ar value +.Bk +.Ar device +.Ek +.Nm +.Op Fl vh +.Fl m Ar msr Ns &= Ns Ar mask +.Bk +.Ar device +.Ek +.Nm +.Op Fl vh +.Fl m Ar msr Ns |= Ns Ar mask .Bk .Ar device .Ek @@ -67,8 +85,32 @@ The following options are available: Where to look for microcode images. The option can be specified multiple times. .It Fl m Ar msr Ns Op = Ns Ar value -Read/write the specified MSR. -Both the MSR and the value should be given as a hex number. +Show value of the specified MSR. +MSR register number should be given as a hexadecimal number. +.It Fl m Ar msr Ns = Ns Ar value +Store the +.Ar value +in the specified MSR register. +The +.Ar value +argument can be prefixed with ~ operator. +In this case the inverted value of argument will be stored in the register. +.It Fl m Ar msr Ns &= Ns Ar mask +Store the result of bitwise AND operation between +.Ar mask +and the current MSR value in the MSR register. +The +.Ar mask +argument can be prefixed with ~ operator. +In this case the inverted value of mask will be used. +.It Fl m Ar msr Ns |= Ns Ar mask +Store the result of bitwise OR operation between +.Ar mask +and the current MSR value in the MSR register. +The +.Ar mask +argument can be prefixed with ~ operator. +In this case the inverted value of mask will be used. .It Fl i Ar level Retrieve CPUID info. Level should be given as a hex number. @@ -94,7 +136,15 @@ will read the contents of TSC MSR from C .Pp To set the CPU 0 TSC MSR register value to 0x1 issue .Pp -.Dq Li "cpucontrol -m 0x10=0x1 /dev/cpuctl0" +.Dq Li "cpucontrol -m 0x10=0x1 /dev/cpuctl0" . +.Pp +The following command will clear the second bit of TSC register: +.Pp +.Dq Li "cpucontrol -m 0x10&=~0x02 /dev/cpuctl0" . +.Pp +The following command will set the forth and second bit of TSC register: +.Pp +.Dq Li "cpucontrol -m 0x10|=0x0a /dev/cpuctl0" . .Pp The command .Pp Modified: head/usr.sbin/cpucontrol/cpucontrol.c ============================================================================== --- head/usr.sbin/cpucontrol/cpucontrol.c Tue Jun 30 11:16:32 2009 (r195188) +++ head/usr.sbin/cpucontrol/cpucontrol.c Tue Jun 30 12:35:47 2009 (r195189) @@ -60,6 +60,12 @@ int verbosity_level = 0; #define FLAG_M 0x02 #define FLAG_U 0x04 +#define OP_INVAL 0x00 +#define OP_READ 0x01 +#define OP_WRITE 0x02 +#define OP_OR 0x04 +#define OP_AND 0x08 + #define HIGH(val) (uint32_t)(((val) >> 32) & 0xffffffff) #define LOW(val) (uint32_t)((val) & 0xffffffff) @@ -166,28 +172,64 @@ do_msr(const char *cmdarg, const char *d { unsigned int msr; cpuctl_msr_args_t args; + size_t len; + uint64_t data = 0; + unsigned long command; + int do_invert = 0, op; int fd, error; - int wr = 0; - char *p; char *endptr; + char *p; assert(cmdarg != NULL); assert(dev != NULL); + len = strlen(cmdarg); + if (len == 0) { + WARNX(0, "MSR register expected"); + usage(); + /* NOTREACHED */ + } - p = strchr(cmdarg, '='); - if (p != NULL) { - wr = 1; - *p++ = '\0'; - args.data = strtoull(p, &endptr, 16); - if (*p == '\0' || *endptr != '\0') { - WARNX(0, "incorrect MSR value: %s", p); - usage(); - /* NOTREACHED */ + /* + * Parse command string. + */ + msr = strtoul(cmdarg, &endptr, 16); + switch (*endptr) { + case '\0': + op = OP_READ; + break; + case '=': + op = OP_WRITE; + break; + case '&': + op = OP_AND; + endptr++; + break; + case '|': + op = OP_OR; + endptr++; + break; + default: + op = OP_INVAL; + } + if (op != OP_READ) { /* Complex operation. */ + if (*endptr != '=') + op = OP_INVAL; + else { + p = ++endptr; + if (*p == '~') { + do_invert = 1; + p++; + } + data = strtoull(p, &endptr, 16); + if (*p == '\0' || *endptr != '\0') { + WARNX(0, "argument required: %s", cmdarg); + usage(); + /* NOTREACHED */ + } } } - msr = strtoul(cmdarg, &endptr, 16); - if (*cmdarg == '\0' || *endptr != '\0') { - WARNX(0, "incorrect MSR register: %s", cmdarg); + if (op == OP_INVAL) { + WARNX(0, "invalid operator: %s", cmdarg); usage(); /* NOTREACHED */ } @@ -196,20 +238,39 @@ do_msr(const char *cmdarg, const char *d * Fill ioctl argument structure. */ args.msr = msr; - fd = open(dev, wr == 0 ? O_RDONLY : O_WRONLY); + if ((do_invert != 0) ^ (op == OP_AND)) + args.data = ~data; + else + args.data = data; + switch (op) { + case OP_READ: + command = CPUCTL_RDMSR; + break; + case OP_WRITE: + command = CPUCTL_WRMSR; + break; + case OP_OR: + command = CPUCTL_MSRSBIT; + break; + case OP_AND: + command = CPUCTL_MSRCBIT; + break; + default: + abort(); + } + fd = open(dev, op == OP_READ ? O_RDONLY : O_WRONLY); if (fd < 0) { WARN(0, "error opening %s for %s", dev, - wr == 0 ? "reading" : "writing"); + op == OP_READ ? "reading" : "writing"); return (1); } - error = ioctl(fd, wr == 0 ? CPUCTL_RDMSR : CPUCTL_WRMSR, &args); + error = ioctl(fd, command, &args); if (error < 0) { - WARN(0, "ioctl(%s, %s)", dev, - wr == 0 ? "CPUCTL_RDMSR" : "CPUCTL_WRMSR"); + WARN(0, "ioctl(%s, %lu)", dev, command); close(fd); return (1); } - if (wr == 0) + if (op == OP_READ) fprintf(stdout, "MSR 0x%x: 0x%.8x 0x%.8x\n", msr, HIGH(args.data), LOW(args.data)); close(fd);
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