Date: Sun, 02 Feb 2003 00:40:02 -0700 From: "Justin T. Gibbs" <gibbs@scsiguy.com> To: "Alan L. Cox" <alc@imimic.com> Cc: cvs-all@FreeBSD.org Subject: Re: cvs commit: src/sys/i386/i386 identcpu.c initcpu.c locore.s Message-ID: <385740000.1044171602@aslan.scsiguy.com> In-Reply-To: <3E3CC4A1.BBFD203A@imimic.com> References: <20030125021907.51B482A89E@canning.wemm.org> <3E32F7C2.C251040@imimic.com> <14020000.1044124868@aslan.scsiguy.com> <3E3CC4A1.BBFD203A@imimic.com>
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> "Justin T. Gibbs" wrote: >> >> > Does anyone here know what needs to be done in terms of saving and >> > restoring SSE/SSE2 state in order to use non-temporal, i.e., >> > not-cached, stores in the idle time page zeroing code? >> >> I don't know if he used SSE/SSE2 or not, but thorpej modified NetBSD's >> page zeroing code to avoid touching the cache well over a year ago. >> You might look at what they are doing. >> > > I just looked at a NetBSD's sys/arch/i386/i386/pmap.c. > pmap_pageidlezero() didn't use SSE/SSE2. Am I looking in the wrong > place? > > Alan I don't believe that NetBSD have ever used SSE/SSE2. From looking at the history of pmap.c, it looks like they used to just map the page into a PTE with PG_N set. A commit entry that removes this changs claims that this is no longer necessary due to page coloring?? Perhaps the remapping was too expensive? I'm sure you can figure out their intent from the revision history: http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/arch/i386/i386/ Since SSE/SSE2 is not available on all processors it may be worthwhile to explore varied ways to get uncached zeroing depending on processor type. -- Justin To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe cvs-all" in the body of the message
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