Date: Tue, 15 Jan 2002 17:21:37 -0800 (PST) From: John Baldwin <jhb@FreeBSD.org> To: Peter Jeremy <peter.jeremy@alcatel.com.au> Cc: arch@FreeBSD.ORG, Thomas Hurst <tom.hurst@clara.net>, "James E. Housley" <jeh@FreeBSD.ORG>, Bosko Milekic <bmilekic@technokratis.com>, Michal Mertl <mime@traveller.cz>, Terry Lambert <tlambert2@mindspring.com> Subject: Re: 64 bit counters again Message-ID: <XFMail.020115172137.jhb@FreeBSD.org> In-Reply-To: <20020116120611.A72285@gsmx07.alcatel.com.au>
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On 16-Jan-02 Peter Jeremy wrote: > For the read case, the reader uses something like: > > loop: movl 4(mem),%edx > movl (mem),%eax > cmpl 4(mem),%edx > jnz loop > > If an interrupt updates the MSW then you take another pass around the > loop, otherwise you always read the correct value. > > For the SMP case, you either need to use locks or you need to use > per-CPU counters. (And the per-CPU counters can be read by another > CPU using the above trick). Well, SMP on Pentium's maybe, but not on Alpha, sparc64, or ia64, all of which support OOE and looser memory models than x86, meaning that you really need locks unless you are going to have 386-specific code all over the place. I suppose you can wrap it behind an MI API but that seems like a lot of work for fairly small gain that can end up making the code uglier. -- John Baldwin <jhb@FreeBSD.org> <>< http://www.FreeBSD.org/~jhb/ "Power Users Use the Power to Serve!" - http://www.FreeBSD.org/ To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-arch" in the body of the message
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