Date: Mon, 3 Feb 2020 13:47:41 +0000 (UTC) From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r357443 - head/sys/arm64/arm64 Message-ID: <202002031347.013DlfWZ056457@repo.freebsd.org>
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Author: andrew Date: Mon Feb 3 13:47:41 2020 New Revision: 357443 URL: https://svnweb.freebsd.org/changeset/base/357443 Log: Disable the use of the quantum cache in the GICv3 ITS This uses UMA to allocate space. It causes issues when there are multiple ITS devices in the system where interrupts are not allocated from a low address on some interrupt controllers. Disabling the quantum cache fixes this on the Neoverse N1 SDP. MFC after: 2 weeks Sponsored by: DARPA, AFRL Modified: head/sys/arm64/arm64/gicv3_its.c Modified: head/sys/arm64/arm64/gicv3_its.c ============================================================================== --- head/sys/arm64/arm64/gicv3_its.c Mon Feb 3 11:33:33 2020 (r357442) +++ head/sys/arm64/arm64/gicv3_its.c Mon Feb 3 13:47:41 2020 (r357443) @@ -800,7 +800,7 @@ gicv3_its_attach(device_t dev) * system. */ sc->sc_irq_alloc = vmem_create("GICv3 ITS IRQs", 0, - gicv3_get_nirqs(dev), 1, 1, M_FIRSTFIT | M_WAITOK); + gicv3_get_nirqs(dev), 1, 0, M_FIRSTFIT | M_WAITOK); sc->sc_irqs = malloc(sizeof(*sc->sc_irqs) * sc->sc_irq_length, M_GICV3_ITS, M_WAITOK | M_ZERO);
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