Date: Fri, 19 Jan 2024 16:33:33 GMT From: Alexander Motin <mav@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org Subject: git: 512235a1d36d - stable/14 - ig4: Fix FIFO depths detection Message-ID: <202401191633.40JGXXDl025889@gitrepo.freebsd.org>
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The branch stable/14 has been updated by mav: URL: https://cgit.FreeBSD.org/src/commit/?id=512235a1d36dd0a855e8a4d3e876100b5f67b3af commit 512235a1d36dd0a855e8a4d3e876100b5f67b3af Author: Alexander Motin <mav@FreeBSD.org> AuthorDate: 2023-12-24 00:02:49 +0000 Commit: Alexander Motin <mav@FreeBSD.org> CommitDate: 2024-01-19 16:33:10 +0000 ig4: Fix FIFO depths detection At least on my Tiger Lake-LP queue depth detection failed before the ig4iic_set_config() call, resulting in no FIFO use. Moving it after solves the problem, getting proper 64 bytes size. On my Dell XPS 13 9310 with iichid(4) touchscreen and touchpad this by few times reduces context switch rate in the driver, and probably also improves the I2C bus utilization. MFC after: 1 month (cherry picked from commit 9c9d7fdd9f0041783955c5f540ac55a900877c0c) --- sys/dev/ichiic/ig4_iic.c | 50 ++++++++++++++++++++++++++++++------------------ 1 file changed, 31 insertions(+), 19 deletions(-) diff --git a/sys/dev/ichiic/ig4_iic.c b/sys/dev/ichiic/ig4_iic.c index 195bca62928a..3a3271454738 100644 --- a/sys/dev/ichiic/ig4_iic.c +++ b/sys/dev/ichiic/ig4_iic.c @@ -847,23 +847,6 @@ ig4iic_get_config(ig4iic_softc_t *sc) sc->cfg.txfifo_depth = IG4_PARAM1_TXFIFO_DEPTH(v); if (IG4_PARAM1_RXFIFO_DEPTH(v) != 0) sc->cfg.rxfifo_depth = IG4_PARAM1_RXFIFO_DEPTH(v); - } else { - /* - * Hardware does not allow FIFO Threshold Levels value to be - * set larger than the depth of the buffer. If an attempt is - * made to do that, the actual value set will be the maximum - * depth of the buffer. - */ - v = reg_read(sc, IG4_REG_TX_TL); - reg_write(sc, IG4_REG_TX_TL, v | IG4_FIFO_MASK); - sc->cfg.txfifo_depth = - (reg_read(sc, IG4_REG_TX_TL) & IG4_FIFO_MASK) + 1; - reg_write(sc, IG4_REG_TX_TL, v); - v = reg_read(sc, IG4_REG_RX_TL); - reg_write(sc, IG4_REG_RX_TL, v | IG4_FIFO_MASK); - sc->cfg.rxfifo_depth = - (reg_read(sc, IG4_REG_RX_TL) & IG4_FIFO_MASK) + 1; - reg_write(sc, IG4_REG_RX_TL, v); } /* Override hardware config with IC_clock-based counter values */ @@ -915,8 +898,6 @@ ig4iic_get_config(ig4iic_softc_t *sc) printf(" Fast: 0x%04hx:0x%04hx:0x%04hx\n", sc->cfg.fs_scl_hcnt, sc->cfg.fs_scl_lcnt, sc->cfg.fs_sda_hold); - printf(" FIFO: RX:0x%04x: TX:0x%04x\n", - sc->cfg.rxfifo_depth, sc->cfg.txfifo_depth); } } @@ -1012,6 +993,36 @@ ig4iic_set_config(ig4iic_softc_t *sc, bool reset) return (0); } +static void +ig4iic_get_fifo(ig4iic_softc_t *sc) +{ + uint32_t v; + + /* + * Hardware does not allow FIFO Threshold Levels value to be set larger + * than the depth of the buffer. If an attempt is made to do that, the + * actual value set will be the maximum depth of the buffer. + */ + if (sc->cfg.txfifo_depth == 0) { + v = reg_read(sc, IG4_REG_TX_TL); + reg_write(sc, IG4_REG_TX_TL, v | IG4_FIFO_MASK); + sc->cfg.txfifo_depth = + (reg_read(sc, IG4_REG_TX_TL) & IG4_FIFO_MASK) + 1; + reg_write(sc, IG4_REG_TX_TL, v); + } + if (sc->cfg.rxfifo_depth == 0) { + v = reg_read(sc, IG4_REG_RX_TL); + reg_write(sc, IG4_REG_RX_TL, v | IG4_FIFO_MASK); + sc->cfg.rxfifo_depth = + (reg_read(sc, IG4_REG_RX_TL) & IG4_FIFO_MASK) + 1; + reg_write(sc, IG4_REG_RX_TL, v); + } + if (bootverbose) { + printf(" FIFO: RX:0x%04x: TX:0x%04x\n", + sc->cfg.rxfifo_depth, sc->cfg.txfifo_depth); + } +} + /* * Called from ig4iic_pci_attach/detach() */ @@ -1028,6 +1039,7 @@ ig4iic_attach(ig4iic_softc_t *sc) error = ig4iic_set_config(sc, IG4_HAS_ADDREGS(sc->version)); if (error) goto done; + ig4iic_get_fifo(sc); sc->iicbus = device_add_child(sc->dev, "iicbus", -1); if (sc->iicbus == NULL) {
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