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Date:      Mon, 19 Mar 2018 18:59:15 +0000 (UTC)
From:      Ruslan Bukin <br@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r331220 - in head/contrib/processor-trace: . include libipt libipt/include
Message-ID:  <201803191859.w2JIxF9s063687@repo.freebsd.org>

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Author: br
Date: Mon Mar 19 18:59:15 2018
New Revision: 331220
URL: https://svnweb.freebsd.org/changeset/base/331220

Log:
  Import Intel Processor Trace decoder library from
  vendor/processor-trace/24982c1a6fce48f1e416461d42899805f74fbb26
  
  Sponsored by:	DARPA, AFRL

Added:
  head/contrib/processor-trace/
  head/contrib/processor-trace/include/
     - copied from r331219, vendor/processor-trace/24982c1a6fce48f1e416461d42899805f74fbb26/include/
  head/contrib/processor-trace/libipt/
     - copied from r331219, vendor/processor-trace/24982c1a6fce48f1e416461d42899805f74fbb26/libipt/
  head/contrib/processor-trace/libipt/include/intel-pt.h
     - copied unchanged from r331219, vendor/processor-trace/24982c1a6fce48f1e416461d42899805f74fbb26/libipt/include/intel-pt.h.in

Copied: head/contrib/processor-trace/libipt/include/intel-pt.h (from r331219, vendor/processor-trace/24982c1a6fce48f1e416461d42899805f74fbb26/libipt/include/intel-pt.h.in)
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ head/contrib/processor-trace/libipt/include/intel-pt.h	Mon Mar 19 18:59:15 2018	(r331220, copy of r331219, vendor/processor-trace/24982c1a6fce48f1e416461d42899805f74fbb26/libipt/include/intel-pt.h.in)
@@ -0,0 +1,2463 @@
+/*
+ * Copyright (c) 2013-2018, Intel Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *  * Neither the name of Intel Corporation nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef INTEL_PT_H
+#define INTEL_PT_H
+
+#include <stdint.h>
+#include <string.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Intel(R) Processor Trace (Intel PT) decoder library.
+ *
+ * This file is logically structured into the following sections:
+ *
+ * - Version
+ * - Errors
+ * - Configuration
+ * - Packet encoder / decoder
+ * - Query decoder
+ * - Traced image
+ * - Instruction flow decoder
+ * - Block decoder
+ */
+
+
+
+struct pt_encoder;
+struct pt_packet_decoder;
+struct pt_query_decoder;
+struct pt_insn_decoder;
+struct pt_block_decoder;
+
+
+
+/* A macro to mark functions as exported. */
+#ifndef pt_export
+#  if defined(__GNUC__)
+#    define pt_export __attribute__((visibility("default")))
+#  elif defined(_MSC_VER)
+#    define pt_export __declspec(dllimport)
+#  else
+#    error "unknown compiler"
+#  endif
+#endif
+
+
+
+/* Version. */
+
+
+/** The header version. */
+#define LIBIPT_VERSION_MAJOR ${PT_VERSION_MAJOR}
+#define LIBIPT_VERSION_MINOR ${PT_VERSION_MINOR}
+
+#define LIBIPT_VERSION ((LIBIPT_VERSION_MAJOR << 8) + LIBIPT_VERSION_MINOR)
+
+
+/** The library version. */
+struct pt_version {
+	/** Major version number. */
+	uint8_t major;
+
+	/** Minor version number. */
+	uint8_t minor;
+
+	/** Reserved bits. */
+	uint16_t reserved;
+
+	/** Build number. */
+	uint32_t build;
+
+	/** Version extension. */
+	const char *ext;
+};
+
+
+/** Return the library version. */
+extern pt_export struct pt_version pt_library_version(void);
+
+
+
+/* Errors. */
+
+
+
+/** Error codes. */
+enum pt_error_code {
+	/* No error. Everything is OK. */
+	pte_ok,
+
+	/* Internal decoder error. */
+	pte_internal,
+
+	/* Invalid argument. */
+	pte_invalid,
+
+	/* Decoder out of sync. */
+	pte_nosync,
+
+	/* Unknown opcode. */
+	pte_bad_opc,
+
+	/* Unknown payload. */
+	pte_bad_packet,
+
+	/* Unexpected packet context. */
+	pte_bad_context,
+
+	/* Decoder reached end of trace stream. */
+	pte_eos,
+
+	/* No packet matching the query to be found. */
+	pte_bad_query,
+
+	/* Decoder out of memory. */
+	pte_nomem,
+
+	/* Bad configuration. */
+	pte_bad_config,
+
+	/* There is no IP. */
+	pte_noip,
+
+	/* The IP has been suppressed. */
+	pte_ip_suppressed,
+
+	/* There is no memory mapped at the requested address. */
+	pte_nomap,
+
+	/* An instruction could not be decoded. */
+	pte_bad_insn,
+
+	/* No wall-clock time is available. */
+	pte_no_time,
+
+	/* No core:bus ratio available. */
+	pte_no_cbr,
+
+	/* Bad traced image. */
+	pte_bad_image,
+
+	/* A locking error. */
+	pte_bad_lock,
+
+	/* The requested feature is not supported. */
+	pte_not_supported,
+
+	/* The return address stack is empty. */
+	pte_retstack_empty,
+
+	/* A compressed return is not indicated correctly by a taken branch. */
+	pte_bad_retcomp,
+
+	/* The current decoder state does not match the state in the trace. */
+	pte_bad_status_update,
+
+	/* The trace did not contain an expected enabled event. */
+	pte_no_enable,
+
+	/* An event was ignored. */
+	pte_event_ignored,
+
+	/* Something overflowed. */
+	pte_overflow,
+
+	/* A file handling error. */
+	pte_bad_file,
+
+	/* Unknown cpu. */
+	pte_bad_cpu
+};
+
+
+/** Decode a function return value into an pt_error_code. */
+static inline enum pt_error_code pt_errcode(int status)
+{
+	return (status >= 0) ? pte_ok : (enum pt_error_code) -status;
+}
+
+/** Return a human readable error string. */
+extern pt_export const char *pt_errstr(enum pt_error_code);
+
+
+
+/* Configuration. */
+
+
+
+/** A cpu vendor. */
+enum pt_cpu_vendor {
+	pcv_unknown,
+	pcv_intel
+};
+
+/** A cpu identifier. */
+struct pt_cpu {
+	/** The cpu vendor. */
+	enum pt_cpu_vendor vendor;
+
+	/** The cpu family. */
+	uint16_t family;
+
+	/** The cpu model. */
+	uint8_t model;
+
+	/** The stepping. */
+	uint8_t stepping;
+};
+
+/** A collection of Intel PT errata. */
+struct pt_errata {
+	/** BDM70: Intel(R) Processor Trace PSB+ Packets May Contain
+	 *         Unexpected Packets.
+	 *
+	 * Same as: SKD024, SKL021, KBL021.
+	 *
+	 * Some Intel Processor Trace packets should be issued only between
+	 * TIP.PGE and TIP.PGD packets.  Due to this erratum, when a TIP.PGE
+	 * packet is generated it may be preceded by a PSB+ that incorrectly
+	 * includes FUP and MODE.Exec packets.
+	 */
+	uint32_t bdm70:1;
+
+	/** BDM64: An Incorrect LBR or Intel(R) Processor Trace Packet May Be
+	 *         Recorded Following a Transactional Abort.
+	 *
+	 * Use of Intel(R) Transactional Synchronization Extensions (Intel(R)
+	 * TSX) may result in a transactional abort.  If an abort occurs
+	 * immediately following a branch instruction, an incorrect branch
+	 * target may be logged in an LBR (Last Branch Record) or in an Intel(R)
+	 * Processor Trace (Intel(R) PT) packet before the LBR or Intel PT
+	 * packet produced by the abort.
+	 */
+	uint32_t bdm64:1;
+
+	/** SKD007: Intel(R) PT Buffer Overflow May Result in Incorrect Packets.
+	 *
+	 * Same as: SKL049, KBL041.
+	 *
+	 * Under complex micro-architectural conditions, an Intel PT (Processor
+	 * Trace) OVF (Overflow) packet may be issued after the first byte of a
+	 * multi-byte CYC (Cycle Count) packet, instead of any remaining bytes
+	 * of the CYC.
+	 */
+	uint32_t skd007:1;
+
+	/** SKD022: VM Entry That Clears TraceEn May Generate a FUP.
+	 *
+	 * Same as: SKL024, KBL023.
+	 *
+	 * If VM entry clears Intel(R) PT (Intel Processor Trace)
+	 * IA32_RTIT_CTL.TraceEn (MSR 570H, bit 0) while PacketEn is 1 then a
+	 * FUP (Flow Update Packet) will precede the TIP.PGD (Target IP Packet,
+	 * Packet Generation Disable).  VM entry can clear TraceEn if the
+	 * VM-entry MSR-load area includes an entry for the IA32_RTIT_CTL MSR.
+	 */
+	uint32_t skd022:1;
+
+	/** SKD010: Intel(R) PT FUP May be Dropped After OVF.
+	 *
+	 * Same as: SKD014, SKL033, KBL030.
+	 *
+	 * Some Intel PT (Intel Processor Trace) OVF (Overflow) packets may not
+	 * be followed by a FUP (Flow Update Packet) or TIP.PGE (Target IP
+	 * Packet, Packet Generation Enable).
+	 */
+	uint32_t skd010:1;
+
+	/** SKL014: Intel(R) PT TIP.PGD May Not Have Target IP Payload.
+	 *
+	 * Same as: KBL014.
+	 *
+	 * When Intel PT (Intel Processor Trace) is enabled and a direct
+	 * unconditional branch clears IA32_RTIT_STATUS.FilterEn (MSR 571H, bit
+	 * 0), due to this erratum, the resulting TIP.PGD (Target IP Packet,
+	 * Packet Generation Disable) may not have an IP payload with the target
+	 * IP.
+	 */
+	uint32_t skl014:1;
+
+	/** APL12: Intel(R) PT OVF May Be Followed By An Unexpected FUP Packet.
+	 *
+	 * Certain Intel PT (Processor Trace) packets including FUPs (Flow
+	 * Update Packets), should be issued only between TIP.PGE (Target IP
+	 * Packet - Packet Generaton Enable) and TIP.PGD (Target IP Packet -
+	 * Packet Generation Disable) packets.  When outside a TIP.PGE/TIP.PGD
+	 * pair, as a result of IA32_RTIT_STATUS.FilterEn[0] (MSR 571H) being
+	 * cleared, an OVF (Overflow) packet may be unexpectedly followed by a
+	 * FUP.
+	 */
+	uint32_t apl12:1;
+
+	/** APL11: Intel(R) PT OVF Pakcet May Be Followed by TIP.PGD Packet
+	 *
+	 * If Intel PT (Processor Trace) encounters an internal buffer overflow
+	 * and generates an OVF (Overflow) packet just as IA32_RTIT_CTL (MSR
+	 * 570H) bit 0 (TraceEn) is cleared, or during a far transfer that
+	 * causes IA32_RTIT_STATUS.ContextEn[1] (MSR 571H) to be cleared, the
+	 * OVF may be followed by a TIP.PGD (Target Instruction Pointer - Packet
+	 * Generation Disable) packet.
+	 */
+	uint32_t apl11:1;
+
+	/* Reserve a few bytes for the future. */
+	uint32_t reserved[15];
+};
+
+/** A collection of decoder-specific configuration flags. */
+struct pt_conf_flags {
+	/** The decoder variant. */
+	union {
+		/** Flags for the block decoder. */
+		struct {
+			/** End a block after a call instruction. */
+			uint32_t end_on_call:1;
+
+			/** Enable tick events for timing updates. */
+			uint32_t enable_tick_events:1;
+
+			/** End a block after a jump instruction. */
+			uint32_t end_on_jump:1;
+		} block;
+
+		/** Flags for the instruction flow decoder. */
+		struct {
+			/** Enable tick events for timing updates. */
+			uint32_t enable_tick_events:1;
+		} insn;
+
+		/* Reserve a few bytes for future extensions. */
+		uint32_t reserved[4];
+	} variant;
+};
+
+/** The address filter configuration. */
+struct pt_conf_addr_filter {
+	/** The address filter configuration.
+	 *
+	 * This corresponds to the respective fields in IA32_RTIT_CTL MSR.
+	 */
+	union {
+		uint64_t addr_cfg;
+
+		struct {
+			uint32_t addr0_cfg:4;
+			uint32_t addr1_cfg:4;
+			uint32_t addr2_cfg:4;
+			uint32_t addr3_cfg:4;
+		} ctl;
+	} config;
+
+	/** The address ranges configuration.
+	 *
+	 * This corresponds to the IA32_RTIT_ADDRn_A/B MSRs.
+	 */
+	uint64_t addr0_a;
+	uint64_t addr0_b;
+	uint64_t addr1_a;
+	uint64_t addr1_b;
+	uint64_t addr2_a;
+	uint64_t addr2_b;
+	uint64_t addr3_a;
+	uint64_t addr3_b;
+
+	/* Reserve some space. */
+	uint64_t reserved[8];
+};
+
+/** An unknown packet. */
+struct pt_packet_unknown;
+
+/** An Intel PT decoder configuration.
+ */
+struct pt_config {
+	/** The size of the config structure in bytes. */
+	size_t size;
+
+	/** The trace buffer begin address. */
+	uint8_t *begin;
+
+	/** The trace buffer end address. */
+	uint8_t *end;
+
+	/** An optional callback for handling unknown packets.
+	 *
+	 * If \@callback is not NULL, it is called for any unknown opcode.
+	 */
+	struct {
+		/** The callback function.
+		 *
+		 * It shall decode the packet at \@pos into \@unknown.
+		 * It shall return the number of bytes read upon success.
+		 * It shall return a negative pt_error_code otherwise.
+		 * The below context is passed as \@context.
+		 */
+		int (*callback)(struct pt_packet_unknown *unknown,
+				const struct pt_config *config,
+				const uint8_t *pos, void *context);
+
+		/** The user-defined context for this configuration. */
+		void *context;
+	} decode;
+
+	/** The cpu on which Intel PT has been recorded. */
+	struct pt_cpu cpu;
+
+	/** The errata to apply when encoding or decoding Intel PT. */
+	struct pt_errata errata;
+
+	/* The CTC frequency.
+	 *
+	 * This is only required if MTC packets have been enabled in
+	 * IA32_RTIT_CTRL.MTCEn.
+	 */
+	uint32_t cpuid_0x15_eax, cpuid_0x15_ebx;
+
+	/* The MTC frequency as defined in IA32_RTIT_CTL.MTCFreq.
+	 *
+	 * This is only required if MTC packets have been enabled in
+	 * IA32_RTIT_CTRL.MTCEn.
+	 */
+	uint8_t mtc_freq;
+
+	/* The nominal frequency as defined in MSR_PLATFORM_INFO[15:8].
+	 *
+	 * This is only required if CYC packets have been enabled in
+	 * IA32_RTIT_CTRL.CYCEn.
+	 *
+	 * If zero, timing calibration will only be able to use MTC and CYC
+	 * packets.
+	 *
+	 * If not zero, timing calibration will also be able to use CBR
+	 * packets.
+	 */
+	uint8_t nom_freq;
+
+	/** A collection of decoder-specific flags. */
+	struct pt_conf_flags flags;
+
+	/** The address filter configuration. */
+	struct pt_conf_addr_filter addr_filter;
+};
+
+
+/** Zero-initialize an Intel PT configuration. */
+static inline void pt_config_init(struct pt_config *config)
+{
+	memset(config, 0, sizeof(*config));
+
+	config->size = sizeof(*config);
+}
+
+/** Determine errata for a given cpu.
+ *
+ * Updates \@errata based on \@cpu.
+ *
+ * Returns 0 on success, a negative error code otherwise.
+ * Returns -pte_invalid if \@errata or \@cpu is NULL.
+ * Returns -pte_bad_cpu if \@cpu is not known.
+ */
+extern pt_export int pt_cpu_errata(struct pt_errata *errata,
+				   const struct pt_cpu *cpu);
+
+
+
+/* Packet encoder / decoder. */
+
+
+
+/** Intel PT packet types. */
+enum pt_packet_type {
+	/* An invalid packet. */
+	ppt_invalid,
+
+	/* A packet decodable by the optional decoder callback. */
+	ppt_unknown,
+
+	/* Actual packets supported by this library. */
+	ppt_pad,
+	ppt_psb,
+	ppt_psbend,
+	ppt_fup,
+	ppt_tip,
+	ppt_tip_pge,
+	ppt_tip_pgd,
+	ppt_tnt_8,
+	ppt_tnt_64,
+	ppt_mode,
+	ppt_pip,
+	ppt_vmcs,
+	ppt_cbr,
+	ppt_tsc,
+	ppt_tma,
+	ppt_mtc,
+	ppt_cyc,
+	ppt_stop,
+	ppt_ovf,
+	ppt_mnt,
+	ppt_exstop,
+	ppt_mwait,
+	ppt_pwre,
+	ppt_pwrx,
+	ppt_ptw
+};
+
+/** The IP compression. */
+enum pt_ip_compression {
+	/* The bits encode the payload size and the encoding scheme.
+	 *
+	 * No payload.  The IP has been suppressed.
+	 */
+	pt_ipc_suppressed	= 0x0,
+
+	/* Payload: 16 bits.  Update last IP. */
+	pt_ipc_update_16	= 0x01,
+
+	/* Payload: 32 bits.  Update last IP. */
+	pt_ipc_update_32	= 0x02,
+
+	/* Payload: 48 bits.  Sign extend to full address. */
+	pt_ipc_sext_48		= 0x03,
+
+	/* Payload: 48 bits.  Update last IP. */
+	pt_ipc_update_48	= 0x04,
+
+	/* Payload: 64 bits.  Full address. */
+	pt_ipc_full		= 0x06
+};
+
+/** An execution mode. */
+enum pt_exec_mode {
+	ptem_unknown,
+	ptem_16bit,
+	ptem_32bit,
+	ptem_64bit
+};
+
+/** Mode packet leaves. */
+enum pt_mode_leaf {
+	pt_mol_exec		= 0x00,
+	pt_mol_tsx		= 0x20
+};
+
+/** A TNT-8 or TNT-64 packet. */
+struct pt_packet_tnt {
+	/** TNT payload bit size. */
+	uint8_t bit_size;
+
+	/** TNT payload excluding stop bit. */
+	uint64_t payload;
+};
+
+/** A packet with IP payload. */
+struct pt_packet_ip {
+	/** IP compression. */
+	enum pt_ip_compression ipc;
+
+	/** Zero-extended payload ip. */
+	uint64_t ip;
+};
+
+/** A mode.exec packet. */
+struct pt_packet_mode_exec {
+	/** The mode.exec csl bit. */
+	uint32_t csl:1;
+
+	/** The mode.exec csd bit. */
+	uint32_t csd:1;
+};
+
+static inline enum pt_exec_mode
+pt_get_exec_mode(const struct pt_packet_mode_exec *packet)
+{
+	if (packet->csl)
+		return packet->csd ? ptem_unknown : ptem_64bit;
+	else
+		return packet->csd ? ptem_32bit : ptem_16bit;
+}
+
+static inline struct pt_packet_mode_exec
+pt_set_exec_mode(enum pt_exec_mode mode)
+{
+	struct pt_packet_mode_exec packet;
+
+	switch (mode) {
+	default:
+		packet.csl = 1;
+		packet.csd = 1;
+		break;
+
+	case ptem_64bit:
+		packet.csl = 1;
+		packet.csd = 0;
+		break;
+
+	case ptem_32bit:
+		packet.csl = 0;
+		packet.csd = 1;
+		break;
+
+	case ptem_16bit:
+		packet.csl = 0;
+		packet.csd = 0;
+		break;
+	}
+
+	return packet;
+}
+
+/** A mode.tsx packet. */
+struct pt_packet_mode_tsx {
+	/** The mode.tsx intx bit. */
+	uint32_t intx:1;
+
+	/** The mode.tsx abrt bit. */
+	uint32_t abrt:1;
+};
+
+/** A mode packet. */
+struct pt_packet_mode {
+	/** Mode leaf. */
+	enum pt_mode_leaf leaf;
+
+	/** Mode bits. */
+	union {
+		/** Packet: mode.exec. */
+		struct pt_packet_mode_exec exec;
+
+		/** Packet: mode.tsx. */
+		struct pt_packet_mode_tsx tsx;
+	} bits;
+};
+
+/** A PIP packet. */
+struct pt_packet_pip {
+	/** The CR3 value. */
+	uint64_t cr3;
+
+	/** The non-root bit. */
+	uint32_t nr:1;
+};
+
+/** A TSC packet. */
+struct pt_packet_tsc {
+	/** The TSC value. */
+	uint64_t tsc;
+};
+
+/** A CBR packet. */
+struct pt_packet_cbr {
+	/** The core/bus cycle ratio. */
+	uint8_t ratio;
+};
+
+/** A TMA packet. */
+struct pt_packet_tma {
+	/** The crystal clock tick counter value. */
+	uint16_t ctc;
+
+	/** The fast counter value. */
+	uint16_t fc;
+};
+
+/** A MTC packet. */
+struct pt_packet_mtc {
+	/** The crystal clock tick counter value. */
+	uint8_t ctc;
+};
+
+/** A CYC packet. */
+struct pt_packet_cyc {
+	/** The cycle counter value. */
+	uint64_t value;
+};
+
+/** A VMCS packet. */
+struct pt_packet_vmcs {
+       /* The VMCS Base Address (i.e. the shifted payload). */
+	uint64_t base;
+};
+
+/** A MNT packet. */
+struct pt_packet_mnt {
+	/** The raw payload. */
+	uint64_t payload;
+};
+
+/** A EXSTOP packet. */
+struct pt_packet_exstop {
+	/** A flag specifying the binding of the packet:
+	 *
+	 *   set:    binds to the next FUP.
+	 *   clear:  standalone.
+	 */
+	uint32_t ip:1;
+};
+
+/** A MWAIT packet. */
+struct pt_packet_mwait {
+	/** The MWAIT hints (EAX). */
+	uint32_t hints;
+
+	/** The MWAIT extensions (ECX). */
+	uint32_t ext;
+};
+
+/** A PWRE packet. */
+struct pt_packet_pwre {
+	/** The resolved thread C-state. */
+	uint8_t state;
+
+	/** The resolved thread sub C-state. */
+	uint8_t sub_state;
+
+	/** A flag indicating whether the C-state entry was initiated by h/w. */
+	uint32_t hw:1;
+};
+
+/** A PWRX packet. */
+struct pt_packet_pwrx {
+	/** The core C-state at the time of the wake. */
+	uint8_t last;
+
+	/** The deepest core C-state achieved during sleep. */
+	uint8_t deepest;
+
+	/** The wake reason:
+	 *
+	 * - due to external interrupt received.
+	 */
+	uint32_t interrupt:1;
+
+	/** - due to store to monitored address. */
+	uint32_t store:1;
+
+	/** - due to h/w autonomous condition such as HDC. */
+	uint32_t autonomous:1;
+};
+
+/** A PTW packet. */
+struct pt_packet_ptw {
+	/** The raw payload. */
+	uint64_t payload;
+
+	/** The payload size as encoded in the packet. */
+	uint8_t plc;
+
+	/** A flag saying whether a FUP is following PTW that provides
+	 * the IP of the corresponding PTWRITE instruction.
+	 */
+	uint32_t ip:1;
+};
+
+static inline int pt_ptw_size(uint8_t plc)
+{
+	switch (plc) {
+	case 0:
+		return 4;
+
+	case 1:
+		return 8;
+
+	case 2:
+	case 3:
+		return -pte_bad_packet;
+	}
+
+	return -pte_internal;
+}
+
+/** An unknown packet decodable by the optional decoder callback. */
+struct pt_packet_unknown {
+	/** Pointer to the raw packet bytes. */
+	const uint8_t *packet;
+
+	/** Optional pointer to a user-defined structure. */
+	void *priv;
+};
+
+/** An Intel PT packet. */
+struct pt_packet {
+	/** The type of the packet.
+	 *
+	 * This also determines the \@payload field.
+	 */
+	enum pt_packet_type type;
+
+	/** The size of the packet including opcode and payload. */
+	uint8_t size;
+
+	/** Packet specific data. */
+	union {
+		/** Packets: pad, ovf, psb, psbend, stop - no payload. */
+
+		/** Packet: tnt-8, tnt-64. */
+		struct pt_packet_tnt tnt;
+
+		/** Packet: tip, fup, tip.pge, tip.pgd. */
+		struct pt_packet_ip ip;
+
+		/** Packet: mode. */
+		struct pt_packet_mode mode;
+
+		/** Packet: pip. */
+		struct pt_packet_pip pip;
+
+		/** Packet: tsc. */
+		struct pt_packet_tsc tsc;
+
+		/** Packet: cbr. */
+		struct pt_packet_cbr cbr;
+
+		/** Packet: tma. */
+		struct pt_packet_tma tma;
+
+		/** Packet: mtc. */
+		struct pt_packet_mtc mtc;
+
+		/** Packet: cyc. */
+		struct pt_packet_cyc cyc;
+
+		/** Packet: vmcs. */
+		struct pt_packet_vmcs vmcs;
+
+		/** Packet: mnt. */
+		struct pt_packet_mnt mnt;
+
+		/** Packet: exstop. */
+		struct pt_packet_exstop exstop;
+
+		/** Packet: mwait. */
+		struct pt_packet_mwait mwait;
+
+		/** Packet: pwre. */
+		struct pt_packet_pwre pwre;
+
+		/** Packet: pwrx. */
+		struct pt_packet_pwrx pwrx;
+
+		/** Packet: ptw. */
+		struct pt_packet_ptw ptw;
+
+		/** Packet: unknown. */
+		struct pt_packet_unknown unknown;
+	} payload;
+};
+
+
+
+/* Packet encoder. */
+
+
+
+/** Allocate an Intel PT packet encoder.
+ *
+ * The encoder will work on the buffer defined in \@config, it shall contain
+ * raw trace data and remain valid for the lifetime of the encoder.
+ *
+ * The encoder starts at the beginning of the trace buffer.
+ */
+extern pt_export struct pt_encoder *
+pt_alloc_encoder(const struct pt_config *config);
+
+/** Free an Intel PT packet encoder.
+ *
+ * The \@encoder must not be used after a successful return.
+ */
+extern pt_export void pt_free_encoder(struct pt_encoder *encoder);
+
+/** Hard set synchronization point of an Intel PT packet encoder.
+ *
+ * Synchronize \@encoder to \@offset within the trace buffer.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ *
+ * Returns -pte_eos if the given offset is behind the end of the trace buffer.
+ * Returns -pte_invalid if \@encoder is NULL.
+ */
+extern pt_export int pt_enc_sync_set(struct pt_encoder *encoder,
+				     uint64_t offset);
+
+/** Get the current packet encoder position.
+ *
+ * Fills the current \@encoder position into \@offset.
+ *
+ * This is useful for reporting errors.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ *
+ * Returns -pte_invalid if \@encoder or \@offset is NULL.
+ */
+extern pt_export int pt_enc_get_offset(const struct pt_encoder *encoder,
+				       uint64_t *offset);
+
+/* Return a pointer to \@encoder's configuration.
+ *
+ * Returns a non-null pointer on success, NULL if \@encoder is NULL.
+ */
+extern pt_export const struct pt_config *
+pt_enc_get_config(const struct pt_encoder *encoder);
+
+/** Encode an Intel PT packet.
+ *
+ * Writes \@packet at \@encoder's current position in the Intel PT buffer and
+ * advances the \@encoder beyond the written packet.
+ *
+ * The \@packet.size field is ignored.
+ *
+ * In case of errors, the \@encoder is not advanced and nothing is written
+ * into the Intel PT buffer.
+ *
+ * Returns the number of bytes written on success, a negative error code
+ * otherwise.
+ *
+ * Returns -pte_bad_opc if \@packet.type is not known.
+ * Returns -pte_bad_packet if \@packet's payload is invalid.
+ * Returns -pte_eos if \@encoder reached the end of the Intel PT buffer.
+ * Returns -pte_invalid if \@encoder or \@packet is NULL.
+ */
+extern pt_export int pt_enc_next(struct pt_encoder *encoder,
+				 const struct pt_packet *packet);
+
+
+
+/* Packet decoder. */
+
+
+
+/** Allocate an Intel PT packet decoder.
+ *
+ * The decoder will work on the buffer defined in \@config, it shall contain
+ * raw trace data and remain valid for the lifetime of the decoder.
+ *
+ * The decoder needs to be synchronized before it can be used.
+ */
+extern pt_export struct pt_packet_decoder *
+pt_pkt_alloc_decoder(const struct pt_config *config);
+
+/** Free an Intel PT packet decoder.
+ *
+ * The \@decoder must not be used after a successful return.
+ */
+extern pt_export void pt_pkt_free_decoder(struct pt_packet_decoder *decoder);
+
+/** Synchronize an Intel PT packet decoder.
+ *
+ * Search for the next synchronization point in forward or backward direction.
+ *
+ * If \@decoder has not been synchronized, yet, the search is started at the
+ * beginning of the trace buffer in case of forward synchronization and at the
+ * end of the trace buffer in case of backward synchronization.
+ *
+ * Returns zero or a positive value on success, a negative error code otherwise.
+ *
+ * Returns -pte_eos if no further synchronization point is found.
+ * Returns -pte_invalid if \@decoder is NULL.
+ */
+extern pt_export int pt_pkt_sync_forward(struct pt_packet_decoder *decoder);
+extern pt_export int pt_pkt_sync_backward(struct pt_packet_decoder *decoder);
+
+/** Hard set synchronization point of an Intel PT decoder.
+ *
+ * Synchronize \@decoder to \@offset within the trace buffer.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ *
+ * Returns -pte_eos if the given offset is behind the end of the trace buffer.
+ * Returns -pte_invalid if \@decoder is NULL.

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