Date: Wed, 25 Mar 2015 14:05:52 +0000 (UTC) From: Gleb Smirnoff <glebius@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r280614 - in projects/ifnet: . bin/cp bin/mv contrib/gcc/config/aarch64 contrib/llvm/include/llvm/CodeGen contrib/llvm/lib/CodeGen/SelectionDAG contrib/llvm/lib/Target/ARM contrib/llvm/... Message-ID: <201503251405.t2PE5qtQ096002@svn.freebsd.org>
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Author: glebius Date: Wed Mar 25 14:05:51 2015 New Revision: 280614 URL: https://svnweb.freebsd.org/changeset/base/280614 Log: Merge head r257698 through r280575. Added: projects/ifnet/contrib/gcc/config/aarch64/ - copied from r280575, head/contrib/gcc/config/aarch64/ projects/ifnet/contrib/llvm/patches/patch-10-llvm-r230348-arm-fix-bad-ha.diff - copied unchanged from r280575, head/contrib/llvm/patches/patch-10-llvm-r230348-arm-fix-bad-ha.diff projects/ifnet/secure/lib/libcrypto/opensslconf-aarch64.h - copied unchanged from r280575, head/secure/lib/libcrypto/opensslconf-aarch64.h projects/ifnet/sys/arm/broadcom/bcm2835/bcm2836.c - copied unchanged from r280575, head/sys/arm/broadcom/bcm2835/bcm2836.c projects/ifnet/sys/arm/broadcom/bcm2835/bcm2836.h - copied unchanged from r280575, head/sys/arm/broadcom/bcm2835/bcm2836.h projects/ifnet/sys/arm/broadcom/bcm2835/files.bcm2836 - copied unchanged from r280575, head/sys/arm/broadcom/bcm2835/files.bcm2836 projects/ifnet/sys/arm/broadcom/bcm2835/std.bcm2836 - copied unchanged from r280575, head/sys/arm/broadcom/bcm2835/std.bcm2836 projects/ifnet/sys/arm/conf/RPI2 - copied unchanged from r280575, head/sys/arm/conf/RPI2 projects/ifnet/sys/boot/fdt/dts/arm/bcm2836.dtsi - copied unchanged from r280575, head/sys/boot/fdt/dts/arm/bcm2836.dtsi projects/ifnet/sys/boot/fdt/dts/arm/rpi2.dts - copied unchanged from r280575, head/sys/boot/fdt/dts/arm/rpi2.dts Deleted: projects/ifnet/sys/arm/mv/mv_sata.c projects/ifnet/sys/dev/ata/chipsets/ata-adaptec.c projects/ifnet/sys/dev/ata/chipsets/ata-ahci.c projects/ifnet/sys/modules/ata/atapci/chipsets/ataadaptec/ projects/ifnet/sys/modules/ata/atapci/chipsets/ataahci/ Modified: projects/ifnet/UPDATING projects/ifnet/bin/cp/utils.c projects/ifnet/bin/mv/mv.c projects/ifnet/contrib/llvm/include/llvm/CodeGen/CallingConvLower.h projects/ifnet/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp projects/ifnet/contrib/llvm/lib/Target/ARM/ARMCallingConv.h projects/ifnet/contrib/llvm/lib/Target/ARM/ARMCallingConv.td projects/ifnet/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp projects/ifnet/contrib/tzdata/asia projects/ifnet/contrib/tzdata/australasia projects/ifnet/contrib/tzdata/europe projects/ifnet/contrib/tzdata/leap-seconds.list projects/ifnet/contrib/tzdata/northamerica projects/ifnet/contrib/tzdata/southamerica projects/ifnet/include/pthread.h projects/ifnet/include/signal.h projects/ifnet/share/man/man4/ahci.4 projects/ifnet/share/man/man4/ata.4 projects/ifnet/share/man/man4/ixl.4 projects/ifnet/share/man/man4/ixlv.4 projects/ifnet/share/man/man4/mvs.4 projects/ifnet/share/man/man4/siis.4 projects/ifnet/share/man/man4/witness.4 projects/ifnet/sys/amd64/include/vmm.h (contents, props changed) projects/ifnet/sys/amd64/vmm/amd/svm.c projects/ifnet/sys/amd64/vmm/intel/vmx.c projects/ifnet/sys/amd64/vmm/vmm.c projects/ifnet/sys/amd64/vmm/vmm_instruction_emul.c projects/ifnet/sys/arm/arm/swtch.S projects/ifnet/sys/arm/arm/sys_machdep.c projects/ifnet/sys/arm/arm/vm_machdep.c projects/ifnet/sys/arm/broadcom/bcm2835/bcm2835_intr.c projects/ifnet/sys/arm/broadcom/bcm2835/bcm2835_machdep.c projects/ifnet/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c projects/ifnet/sys/arm/broadcom/bcm2835/std.bcm2835 projects/ifnet/sys/arm/broadcom/bcm2835/std.rpi projects/ifnet/sys/arm/conf/RPI-B projects/ifnet/sys/arm/mv/files.mv projects/ifnet/sys/arm64/include/_types.h projects/ifnet/sys/arm64/include/cpu.h projects/ifnet/sys/arm64/include/float.h projects/ifnet/sys/arm64/include/pmap.h projects/ifnet/sys/arm64/include/proc.h projects/ifnet/sys/arm64/include/signal.h projects/ifnet/sys/arm64/include/stdarg.h projects/ifnet/sys/arm64/include/vmparam.h projects/ifnet/sys/boot/forth/check-password.4th projects/ifnet/sys/boot/forth/loader.conf projects/ifnet/sys/cam/cam_xpt.c projects/ifnet/sys/cam/ctl/ctl.c projects/ifnet/sys/conf/NOTES projects/ifnet/sys/conf/files projects/ifnet/sys/conf/options.arm projects/ifnet/sys/dev/ahci/ahci.c projects/ifnet/sys/dev/ahci/ahci_pci.c projects/ifnet/sys/dev/ahci/ahciem.c projects/ifnet/sys/dev/ata/ata-all.c projects/ifnet/sys/dev/ata/ata-all.h projects/ifnet/sys/dev/ata/ata-pci.h projects/ifnet/sys/dev/ata/chipsets/ata-acard.c projects/ifnet/sys/dev/ata/chipsets/ata-acerlabs.c projects/ifnet/sys/dev/ata/chipsets/ata-amd.c projects/ifnet/sys/dev/ata/chipsets/ata-ati.c projects/ifnet/sys/dev/ata/chipsets/ata-cenatek.c projects/ifnet/sys/dev/ata/chipsets/ata-cypress.c projects/ifnet/sys/dev/ata/chipsets/ata-cyrix.c projects/ifnet/sys/dev/ata/chipsets/ata-fsl.c projects/ifnet/sys/dev/ata/chipsets/ata-highpoint.c projects/ifnet/sys/dev/ata/chipsets/ata-intel.c projects/ifnet/sys/dev/ata/chipsets/ata-ite.c projects/ifnet/sys/dev/ata/chipsets/ata-jmicron.c projects/ifnet/sys/dev/ata/chipsets/ata-marvell.c projects/ifnet/sys/dev/ata/chipsets/ata-micron.c projects/ifnet/sys/dev/ata/chipsets/ata-national.c projects/ifnet/sys/dev/ata/chipsets/ata-netcell.c projects/ifnet/sys/dev/ata/chipsets/ata-nvidia.c projects/ifnet/sys/dev/ata/chipsets/ata-promise.c projects/ifnet/sys/dev/ata/chipsets/ata-serverworks.c projects/ifnet/sys/dev/ata/chipsets/ata-siliconimage.c projects/ifnet/sys/dev/ata/chipsets/ata-sis.c projects/ifnet/sys/dev/ata/chipsets/ata-via.c projects/ifnet/sys/dev/cxgbe/t4_main.c projects/ifnet/sys/dev/mvs/mvs.c projects/ifnet/sys/dev/mvs/mvs_pci.c projects/ifnet/sys/dev/mvs/mvs_soc.c projects/ifnet/sys/dev/netmap/ixgbe_netmap.h projects/ifnet/sys/dev/sfxge/common/efsys.h projects/ifnet/sys/dev/sfxge/common/efx_mcdi.c projects/ifnet/sys/dev/sfxge/sfxge.c projects/ifnet/sys/dev/sfxge/sfxge.h projects/ifnet/sys/dev/sfxge/sfxge_port.c projects/ifnet/sys/dev/sfxge/sfxge_rx.c projects/ifnet/sys/dev/sfxge/sfxge_tx.c projects/ifnet/sys/dev/sfxge/sfxge_tx.h projects/ifnet/sys/dev/siis/siis.c projects/ifnet/sys/dev/sound/pcm/channel.c projects/ifnet/sys/dev/sound/pcm/dsp.c projects/ifnet/sys/dev/sound/pcm/feeder_eq.c projects/ifnet/sys/dev/sound/pcm/feeder_rate.c projects/ifnet/sys/dev/sound/pcm/mixer.c projects/ifnet/sys/dev/sound/pcm/sndstat.c projects/ifnet/sys/dev/sound/pcm/sound.c projects/ifnet/sys/dev/sound/pcm/vchan.c projects/ifnet/sys/dev/sound/usb/uaudio.c projects/ifnet/sys/kern/kern_descrip.c projects/ifnet/sys/kern/kern_jail.c projects/ifnet/sys/kern/kern_sig.c projects/ifnet/sys/kern/kern_sysctl.c projects/ifnet/sys/modules/ata/atapci/chipsets/Makefile projects/ifnet/sys/modules/dtb/rpi/Makefile projects/ifnet/sys/modules/sfxge/Makefile projects/ifnet/sys/netinet/sctp_indata.c projects/ifnet/sys/netinet/sctp_output.c projects/ifnet/sys/netinet/sctp_pcb.c projects/ifnet/sys/netinet/sctp_usrreq.c projects/ifnet/sys/netinet/sctputil.c projects/ifnet/sys/netinet/siftr.c projects/ifnet/sys/netinet6/in6.h projects/ifnet/sys/netinet6/in6_var.h projects/ifnet/sys/vm/vm_page.c projects/ifnet/sys/x86/iommu/intel_gas.c projects/ifnet/sys/x86/iommu/intel_idpgtbl.c projects/ifnet/usr.bin/xlint/arch/sparc64/targparam.h projects/ifnet/usr.bin/xlint/common/lint.h projects/ifnet/usr.bin/xlint/common/mem.c projects/ifnet/usr.bin/xlint/lint1/cgram.y projects/ifnet/usr.bin/xlint/lint1/decl.c projects/ifnet/usr.bin/xlint/lint1/emit1.c projects/ifnet/usr.bin/xlint/lint1/err.c projects/ifnet/usr.bin/xlint/lint1/externs1.h projects/ifnet/usr.bin/xlint/lint1/func.c projects/ifnet/usr.bin/xlint/lint1/init.c projects/ifnet/usr.bin/xlint/lint1/lint1.h projects/ifnet/usr.bin/xlint/lint1/main1.c projects/ifnet/usr.bin/xlint/lint1/makeman projects/ifnet/usr.bin/xlint/lint1/scan.l projects/ifnet/usr.bin/xlint/lint1/tree.c projects/ifnet/usr.bin/xlint/lint2/read.c projects/ifnet/usr.bin/xlint/xlint/lint.1 projects/ifnet/usr.bin/xlint/xlint/xlint.c Directory Properties: projects/ifnet/ (props changed) projects/ifnet/contrib/gcc/ (props changed) projects/ifnet/contrib/llvm/ (props changed) projects/ifnet/contrib/tzdata/ (props changed) projects/ifnet/include/ (props changed) projects/ifnet/share/ (props changed) projects/ifnet/share/man/man4/ (props changed) projects/ifnet/sys/ (props changed) projects/ifnet/sys/amd64/vmm/ (props changed) projects/ifnet/sys/boot/ (props changed) projects/ifnet/sys/conf/ (props changed) Modified: projects/ifnet/UPDATING ============================================================================== --- projects/ifnet/UPDATING Wed Mar 25 13:57:54 2015 (r280613) +++ projects/ifnet/UPDATING Wed Mar 25 14:05:51 2015 (r280614) @@ -31,6 +31,12 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 11 disable the most expensive debugging functionality run "ln -s 'abort:false,junk:false' /etc/malloc.conf".) +20150324: + From legacy ata(4) driver was removed support for SATA controllers + supported by more functional drivers ahci(4), siis(4) and mvs(4). + Kernel modules ataahci and ataadaptec were removed completely, + replaced by ahci and mvs modules respectively. + 20150315: Clang, llvm and lldb have been upgraded to 3.6.0 release. Please see the 20141231 entry below for information about prerequisites and Modified: projects/ifnet/bin/cp/utils.c ============================================================================== --- projects/ifnet/bin/cp/utils.c Wed Mar 25 13:57:54 2015 (r280613) +++ projects/ifnet/bin/cp/utils.c Wed Mar 25 14:05:51 2015 (r280614) @@ -342,7 +342,7 @@ setfile(struct stat *fs, int fd) tspec[0] = fs->st_atim; tspec[1] = fs->st_mtim; - if (utimensat(AT_FDCWD, to.p_path, tspec, + if (fdval ? futimens(fd, tspec) : utimensat(AT_FDCWD, to.p_path, tspec, islink ? AT_SYMLINK_NOFOLLOW : 0)) { warn("utimensat: %s", to.p_path); rval = 1; Modified: projects/ifnet/bin/mv/mv.c ============================================================================== --- projects/ifnet/bin/mv/mv.c Wed Mar 25 13:57:54 2015 (r280613) +++ projects/ifnet/bin/mv/mv.c Wed Mar 25 14:05:51 2015 (r280614) @@ -352,7 +352,7 @@ err: if (unlink(to)) ts[0] = sbp->st_atim; ts[1] = sbp->st_mtim; - if (utimensat(AT_FDCWD, to, ts, 0)) + if (futimens(to_fd, ts)) warn("%s: set times", to); if (close(to_fd)) { Modified: projects/ifnet/contrib/llvm/include/llvm/CodeGen/CallingConvLower.h ============================================================================== --- projects/ifnet/contrib/llvm/include/llvm/CodeGen/CallingConvLower.h Wed Mar 25 13:57:54 2015 (r280613) +++ projects/ifnet/contrib/llvm/include/llvm/CodeGen/CallingConvLower.h Wed Mar 25 14:05:51 2015 (r280614) @@ -122,8 +122,8 @@ public: // There is no need to differentiate between a pending CCValAssign and other // kinds, as they are stored in a different list. static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT, - LocInfo HTP) { - return getReg(ValNo, ValVT, 0, LocVT, HTP); + LocInfo HTP, unsigned ExtraInfo = 0) { + return getReg(ValNo, ValVT, ExtraInfo, LocVT, HTP); } void convertToReg(unsigned RegNo) { @@ -146,6 +146,7 @@ public: unsigned getLocReg() const { assert(isRegLoc()); return Loc; } unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; } + unsigned getExtraInfo() const { return Loc; } MVT getLocVT() const { return LocVT; } LocInfo getLocInfo() const { return HTP; } Modified: projects/ifnet/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp ============================================================================== --- projects/ifnet/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Mar 25 13:57:54 2015 (r280613) +++ projects/ifnet/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Mar 25 14:05:51 2015 (r280614) @@ -7429,11 +7429,8 @@ TargetLowering::LowerCallTo(TargetLoweri } if (Args[i].isNest) Flags.setNest(); - if (NeedsRegBlock) { + if (NeedsRegBlock) Flags.setInConsecutiveRegs(); - if (Value == NumValues - 1) - Flags.setInConsecutiveRegsLast(); - } Flags.setOrigAlign(OriginalAlignment); MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT); @@ -7482,6 +7479,9 @@ TargetLowering::LowerCallTo(TargetLoweri CLI.Outs.push_back(MyFlags); CLI.OutVals.push_back(Parts[j]); } + + if (NeedsRegBlock && Value == NumValues - 1) + CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast(); } } @@ -7696,11 +7696,8 @@ void SelectionDAGISel::LowerArguments(co } if (F.getAttributes().hasAttribute(Idx, Attribute::Nest)) Flags.setNest(); - if (NeedsRegBlock) { + if (NeedsRegBlock) Flags.setInConsecutiveRegs(); - if (Value == NumValues - 1) - Flags.setInConsecutiveRegsLast(); - } Flags.setOrigAlign(OriginalAlignment); MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT); @@ -7715,6 +7712,8 @@ void SelectionDAGISel::LowerArguments(co MyFlags.Flags.setOrigAlign(1); Ins.push_back(MyFlags); } + if (NeedsRegBlock && Value == NumValues - 1) + Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast(); PartBase += VT.getStoreSize(); } } Modified: projects/ifnet/contrib/llvm/lib/Target/ARM/ARMCallingConv.h ============================================================================== --- projects/ifnet/contrib/llvm/lib/Target/ARM/ARMCallingConv.h Wed Mar 25 13:57:54 2015 (r280613) +++ projects/ifnet/contrib/llvm/lib/Target/ARM/ARMCallingConv.h Wed Mar 25 14:05:51 2015 (r280614) @@ -160,6 +160,8 @@ static bool RetCC_ARM_AAPCS_Custom_f64(u State); } +static const uint16_t RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; + static const uint16_t SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, @@ -168,81 +170,114 @@ static const uint16_t DRegList[] = { ARM ARM::D4, ARM::D5, ARM::D6, ARM::D7 }; static const uint16_t QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 }; + // Allocate part of an AAPCS HFA or HVA. We assume that each member of the HA // has InConsecutiveRegs set, and that the last member also has // InConsecutiveRegsLast set. We must process all members of the HA before // we can allocate it, as we need to know the total number of registers that // will be needed in order to (attempt to) allocate a contiguous block. -static bool CC_ARM_AAPCS_Custom_HA(unsigned &ValNo, MVT &ValVT, MVT &LocVT, - CCValAssign::LocInfo &LocInfo, - ISD::ArgFlagsTy &ArgFlags, CCState &State) { - SmallVectorImpl<CCValAssign> &PendingHAMembers = State.getPendingLocs(); +static bool CC_ARM_AAPCS_Custom_Aggregate(unsigned &ValNo, MVT &ValVT, + MVT &LocVT, + CCValAssign::LocInfo &LocInfo, + ISD::ArgFlagsTy &ArgFlags, + CCState &State) { + SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs(); // AAPCS HFAs must have 1-4 elements, all of the same type - assert(PendingHAMembers.size() < 4); - if (PendingHAMembers.size() > 0) - assert(PendingHAMembers[0].getLocVT() == LocVT); + if (PendingMembers.size() > 0) + assert(PendingMembers[0].getLocVT() == LocVT); // Add the argument to the list to be allocated once we know the size of the - // HA - PendingHAMembers.push_back( - CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo)); - - if (ArgFlags.isInConsecutiveRegsLast()) { - assert(PendingHAMembers.size() > 0 && PendingHAMembers.size() <= 4 && - "Homogeneous aggregates must have between 1 and 4 members"); - - // Try to allocate a contiguous block of registers, each of the correct - // size to hold one member. - ArrayRef<uint16_t> RegList; - switch (LocVT.SimpleTy) { - case MVT::f32: - RegList = SRegList; - break; - case MVT::f64: - RegList = DRegList; - break; - case MVT::v2f64: - RegList = QRegList; - break; - default: - llvm_unreachable("Unexpected member type for HA"); - break; - } + // aggregate. Store the type's required alignmnent as extra info for later: in + // the [N x i64] case all trace has been removed by the time we actually get + // to do allocation. + PendingMembers.push_back(CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo, + ArgFlags.getOrigAlign())); + + if (!ArgFlags.isInConsecutiveRegsLast()) + return true; + + // Try to allocate a contiguous block of registers, each of the correct + // size to hold one member. + unsigned Align = std::min(PendingMembers[0].getExtraInfo(), 8U); + + ArrayRef<uint16_t> RegList; + switch (LocVT.SimpleTy) { + case MVT::i32: { + RegList = RRegList; + unsigned RegIdx = State.getFirstUnallocated(RegList.data(), RegList.size()); + + // First consume all registers that would give an unaligned object. Whether + // we go on stack or in regs, no-one will be using them in future. + unsigned RegAlign = RoundUpToAlignment(Align, 4) / 4; + while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) + State.AllocateReg(RegList[RegIdx++]); - unsigned RegResult = - State.AllocateRegBlock(RegList, PendingHAMembers.size()); + break; + } + case MVT::f32: + RegList = SRegList; + break; + case MVT::f64: + RegList = DRegList; + break; + case MVT::v2f64: + RegList = QRegList; + break; + default: + llvm_unreachable("Unexpected member type for block aggregate"); + break; + } - if (RegResult) { - for (SmallVectorImpl<CCValAssign>::iterator It = PendingHAMembers.begin(); - It != PendingHAMembers.end(); ++It) { - It->convertToReg(RegResult); - State.addLoc(*It); - ++RegResult; - } - PendingHAMembers.clear(); - return true; + unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size()); + if (RegResult) { + for (SmallVectorImpl<CCValAssign>::iterator It = PendingMembers.begin(); + It != PendingMembers.end(); ++It) { + It->convertToReg(RegResult); + State.addLoc(*It); + ++RegResult; } + PendingMembers.clear(); + return true; + } - // Register allocation failed, fall back to the stack - - // Mark all VFP regs as unavailable (AAPCS rule C.2.vfp) - for (unsigned regNo = 0; regNo < 16; ++regNo) - State.AllocateReg(SRegList[regNo]); - - unsigned Size = LocVT.getSizeInBits() / 8; - unsigned Align = std::min(Size, 8U); + // Register allocation failed, we'll be needing the stack + unsigned Size = LocVT.getSizeInBits() / 8; + if (LocVT == MVT::i32 && State.getNextStackOffset() == 0) { + // If nothing else has used the stack until this point, a non-HFA aggregate + // can be split between regs and stack. + unsigned RegIdx = State.getFirstUnallocated(RegList.data(), RegList.size()); + for (auto &It : PendingMembers) { + if (RegIdx >= RegList.size()) + It.convertToMem(State.AllocateStack(Size, Size)); + else + It.convertToReg(State.AllocateReg(RegList[RegIdx++])); - for (auto It : PendingHAMembers) { - It.convertToMem(State.AllocateStack(Size, Align)); State.addLoc(It); } - - // All pending members have now been allocated - PendingHAMembers.clear(); + PendingMembers.clear(); + return true; + } else if (LocVT != MVT::i32) + RegList = SRegList; + + // Mark all regs as unavailable (AAPCS rule C.2.vfp for VFP, C.6 for core) + for (auto Reg : RegList) + State.AllocateReg(Reg); + + for (auto &It : PendingMembers) { + It.convertToMem(State.AllocateStack(Size, Align)); + State.addLoc(It); + + // After the first item has been allocated, the rest are packed as tightly + // as possible. (E.g. an incoming i64 would have starting Align of 8, but + // we'll be allocating a bunch of i32 slots). + Align = Size; } - // This will be allocated by the last member of the HA + // All pending members have now been allocated + PendingMembers.clear(); + + // This will be allocated by the last member of the aggregate return true; } Modified: projects/ifnet/contrib/llvm/lib/Target/ARM/ARMCallingConv.td ============================================================================== --- projects/ifnet/contrib/llvm/lib/Target/ARM/ARMCallingConv.td Wed Mar 25 13:57:54 2015 (r280613) +++ projects/ifnet/contrib/llvm/lib/Target/ARM/ARMCallingConv.td Wed Mar 25 14:05:51 2015 (r280614) @@ -175,7 +175,7 @@ def CC_ARM_AAPCS_VFP : CallingConv<[ CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, // HFAs are passed in a contiguous block of registers, or on the stack - CCIfConsecutiveRegs<CCCustom<"CC_ARM_AAPCS_Custom_HA">>, + CCIfConsecutiveRegs<CCCustom<"CC_ARM_AAPCS_Custom_Aggregate">>, CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, Modified: projects/ifnet/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp ============================================================================== --- projects/ifnet/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp Wed Mar 25 13:57:54 2015 (r280613) +++ projects/ifnet/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp Wed Mar 25 14:05:51 2015 (r280614) @@ -11280,7 +11280,9 @@ static bool isHomogeneousAggregate(Type return (Members > 0 && Members <= 4); } -/// \brief Return true if a type is an AAPCS-VFP homogeneous aggregate. +/// \brief Return true if a type is an AAPCS-VFP homogeneous aggregate or one of +/// [N x i32] or [N x i64]. This allows front-ends to skip emitting padding when +/// passing according to AAPCS rules. bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters( Type *Ty, CallingConv::ID CallConv, bool isVarArg) const { if (getEffectiveCallingConv(CallConv, isVarArg) != @@ -11289,7 +11291,9 @@ bool ARMTargetLowering::functionArgument HABaseType Base = HA_UNKNOWN; uint64_t Members = 0; - bool result = isHomogeneousAggregate(Ty, Base, Members); - DEBUG(dbgs() << "isHA: " << result << " "; Ty->dump()); - return result; + bool IsHA = isHomogeneousAggregate(Ty, Base, Members); + DEBUG(dbgs() << "isHA: " << IsHA << " "; Ty->dump()); + + bool IsIntArray = Ty->isArrayTy() && Ty->getArrayElementType()->isIntegerTy(); + return IsHA || IsIntArray; } Copied: projects/ifnet/contrib/llvm/patches/patch-10-llvm-r230348-arm-fix-bad-ha.diff (from r280575, head/contrib/llvm/patches/patch-10-llvm-r230348-arm-fix-bad-ha.diff) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ projects/ifnet/contrib/llvm/patches/patch-10-llvm-r230348-arm-fix-bad-ha.diff Wed Mar 25 14:05:51 2015 (r280614, copy of r280575, head/contrib/llvm/patches/patch-10-llvm-r230348-arm-fix-bad-ha.diff) @@ -0,0 +1,419 @@ +Pull in r230348 from upstream llvm trunk (by Tim Northover): + + ARM: treat [N x i32] and [N x i64] as AAPCS composite types + + The logic is almost there already, with our special homogeneous + aggregate handling. Tweaking it like this allows front-ends to emit + AAPCS compliant code without ever having to count registers or add + discarded padding arguments. + + Only arrays of i32 and i64 are needed to model AAPCS rules, but I + decided to apply the logic to all integer arrays for more consistency. + +This fixes a possible "Unexpected member type for HA" error when +compiling lib/msun/bsdsrc/b_tgamma.c for armv6. + +Reported by: Jakub Palider <jpa@semihalf.com> + +Introduced here: https://svnweb.freebsd.org/changeset/base/280400 + +Index: include/llvm/CodeGen/CallingConvLower.h +=================================================================== +--- include/llvm/CodeGen/CallingConvLower.h ++++ include/llvm/CodeGen/CallingConvLower.h +@@ -122,8 +122,8 @@ class CCValAssign { + // There is no need to differentiate between a pending CCValAssign and other + // kinds, as they are stored in a different list. + static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT, +- LocInfo HTP) { +- return getReg(ValNo, ValVT, 0, LocVT, HTP); ++ LocInfo HTP, unsigned ExtraInfo = 0) { ++ return getReg(ValNo, ValVT, ExtraInfo, LocVT, HTP); + } + + void convertToReg(unsigned RegNo) { +@@ -146,6 +146,7 @@ class CCValAssign { + + unsigned getLocReg() const { assert(isRegLoc()); return Loc; } + unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; } ++ unsigned getExtraInfo() const { return Loc; } + MVT getLocVT() const { return LocVT; } + + LocInfo getLocInfo() const { return HTP; } +Index: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +=================================================================== +--- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp ++++ lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +@@ -7429,11 +7429,8 @@ TargetLowering::LowerCallTo(TargetLowering::CallLo + } + if (Args[i].isNest) + Flags.setNest(); +- if (NeedsRegBlock) { ++ if (NeedsRegBlock) + Flags.setInConsecutiveRegs(); +- if (Value == NumValues - 1) +- Flags.setInConsecutiveRegsLast(); +- } + Flags.setOrigAlign(OriginalAlignment); + + MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT); +@@ -7482,6 +7479,9 @@ TargetLowering::LowerCallTo(TargetLowering::CallLo + CLI.Outs.push_back(MyFlags); + CLI.OutVals.push_back(Parts[j]); + } ++ ++ if (NeedsRegBlock && Value == NumValues - 1) ++ CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast(); + } + } + +@@ -7696,11 +7696,8 @@ void SelectionDAGISel::LowerArguments(const Functi + } + if (F.getAttributes().hasAttribute(Idx, Attribute::Nest)) + Flags.setNest(); +- if (NeedsRegBlock) { ++ if (NeedsRegBlock) + Flags.setInConsecutiveRegs(); +- if (Value == NumValues - 1) +- Flags.setInConsecutiveRegsLast(); +- } + Flags.setOrigAlign(OriginalAlignment); + + MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT); +@@ -7715,6 +7712,8 @@ void SelectionDAGISel::LowerArguments(const Functi + MyFlags.Flags.setOrigAlign(1); + Ins.push_back(MyFlags); + } ++ if (NeedsRegBlock && Value == NumValues - 1) ++ Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast(); + PartBase += VT.getStoreSize(); + } + } +Index: lib/Target/ARM/ARMCallingConv.h +=================================================================== +--- lib/Target/ARM/ARMCallingConv.h ++++ lib/Target/ARM/ARMCallingConv.h +@@ -160,6 +160,8 @@ static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &V + State); + } + ++static const uint16_t RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; ++ + static const uint16_t SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3, + ARM::S4, ARM::S5, ARM::S6, ARM::S7, + ARM::S8, ARM::S9, ARM::S10, ARM::S11, +@@ -168,81 +170,114 @@ static const uint16_t DRegList[] = { ARM::D0, ARM: + ARM::D4, ARM::D5, ARM::D6, ARM::D7 }; + static const uint16_t QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 }; + ++ + // Allocate part of an AAPCS HFA or HVA. We assume that each member of the HA + // has InConsecutiveRegs set, and that the last member also has + // InConsecutiveRegsLast set. We must process all members of the HA before + // we can allocate it, as we need to know the total number of registers that + // will be needed in order to (attempt to) allocate a contiguous block. +-static bool CC_ARM_AAPCS_Custom_HA(unsigned &ValNo, MVT &ValVT, MVT &LocVT, +- CCValAssign::LocInfo &LocInfo, +- ISD::ArgFlagsTy &ArgFlags, CCState &State) { +- SmallVectorImpl<CCValAssign> &PendingHAMembers = State.getPendingLocs(); ++static bool CC_ARM_AAPCS_Custom_Aggregate(unsigned &ValNo, MVT &ValVT, ++ MVT &LocVT, ++ CCValAssign::LocInfo &LocInfo, ++ ISD::ArgFlagsTy &ArgFlags, ++ CCState &State) { ++ SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs(); + + // AAPCS HFAs must have 1-4 elements, all of the same type +- assert(PendingHAMembers.size() < 4); +- if (PendingHAMembers.size() > 0) +- assert(PendingHAMembers[0].getLocVT() == LocVT); ++ if (PendingMembers.size() > 0) ++ assert(PendingMembers[0].getLocVT() == LocVT); + + // Add the argument to the list to be allocated once we know the size of the +- // HA +- PendingHAMembers.push_back( +- CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo)); ++ // aggregate. Store the type's required alignmnent as extra info for later: in ++ // the [N x i64] case all trace has been removed by the time we actually get ++ // to do allocation. ++ PendingMembers.push_back(CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo, ++ ArgFlags.getOrigAlign())); + +- if (ArgFlags.isInConsecutiveRegsLast()) { +- assert(PendingHAMembers.size() > 0 && PendingHAMembers.size() <= 4 && +- "Homogeneous aggregates must have between 1 and 4 members"); ++ if (!ArgFlags.isInConsecutiveRegsLast()) ++ return true; + +- // Try to allocate a contiguous block of registers, each of the correct +- // size to hold one member. +- ArrayRef<uint16_t> RegList; +- switch (LocVT.SimpleTy) { +- case MVT::f32: +- RegList = SRegList; +- break; +- case MVT::f64: +- RegList = DRegList; +- break; +- case MVT::v2f64: +- RegList = QRegList; +- break; +- default: +- llvm_unreachable("Unexpected member type for HA"); +- break; +- } ++ // Try to allocate a contiguous block of registers, each of the correct ++ // size to hold one member. ++ unsigned Align = std::min(PendingMembers[0].getExtraInfo(), 8U); + +- unsigned RegResult = +- State.AllocateRegBlock(RegList, PendingHAMembers.size()); ++ ArrayRef<uint16_t> RegList; ++ switch (LocVT.SimpleTy) { ++ case MVT::i32: { ++ RegList = RRegList; ++ unsigned RegIdx = State.getFirstUnallocated(RegList.data(), RegList.size()); + +- if (RegResult) { +- for (SmallVectorImpl<CCValAssign>::iterator It = PendingHAMembers.begin(); +- It != PendingHAMembers.end(); ++It) { +- It->convertToReg(RegResult); +- State.addLoc(*It); +- ++RegResult; +- } +- PendingHAMembers.clear(); +- return true; +- } ++ // First consume all registers that would give an unaligned object. Whether ++ // we go on stack or in regs, no-one will be using them in future. ++ unsigned RegAlign = RoundUpToAlignment(Align, 4) / 4; ++ while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) ++ State.AllocateReg(RegList[RegIdx++]); + +- // Register allocation failed, fall back to the stack ++ break; ++ } ++ case MVT::f32: ++ RegList = SRegList; ++ break; ++ case MVT::f64: ++ RegList = DRegList; ++ break; ++ case MVT::v2f64: ++ RegList = QRegList; ++ break; ++ default: ++ llvm_unreachable("Unexpected member type for block aggregate"); ++ break; ++ } + +- // Mark all VFP regs as unavailable (AAPCS rule C.2.vfp) +- for (unsigned regNo = 0; regNo < 16; ++regNo) +- State.AllocateReg(SRegList[regNo]); ++ unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size()); ++ if (RegResult) { ++ for (SmallVectorImpl<CCValAssign>::iterator It = PendingMembers.begin(); ++ It != PendingMembers.end(); ++It) { ++ It->convertToReg(RegResult); ++ State.addLoc(*It); ++ ++RegResult; ++ } ++ PendingMembers.clear(); ++ return true; ++ } + +- unsigned Size = LocVT.getSizeInBits() / 8; +- unsigned Align = std::min(Size, 8U); ++ // Register allocation failed, we'll be needing the stack ++ unsigned Size = LocVT.getSizeInBits() / 8; ++ if (LocVT == MVT::i32 && State.getNextStackOffset() == 0) { ++ // If nothing else has used the stack until this point, a non-HFA aggregate ++ // can be split between regs and stack. ++ unsigned RegIdx = State.getFirstUnallocated(RegList.data(), RegList.size()); ++ for (auto &It : PendingMembers) { ++ if (RegIdx >= RegList.size()) ++ It.convertToMem(State.AllocateStack(Size, Size)); ++ else ++ It.convertToReg(State.AllocateReg(RegList[RegIdx++])); + +- for (auto It : PendingHAMembers) { +- It.convertToMem(State.AllocateStack(Size, Align)); + State.addLoc(It); + } ++ PendingMembers.clear(); ++ return true; ++ } else if (LocVT != MVT::i32) ++ RegList = SRegList; + +- // All pending members have now been allocated +- PendingHAMembers.clear(); ++ // Mark all regs as unavailable (AAPCS rule C.2.vfp for VFP, C.6 for core) ++ for (auto Reg : RegList) ++ State.AllocateReg(Reg); ++ ++ for (auto &It : PendingMembers) { ++ It.convertToMem(State.AllocateStack(Size, Align)); ++ State.addLoc(It); ++ ++ // After the first item has been allocated, the rest are packed as tightly ++ // as possible. (E.g. an incoming i64 would have starting Align of 8, but ++ // we'll be allocating a bunch of i32 slots). ++ Align = Size; + } + +- // This will be allocated by the last member of the HA ++ // All pending members have now been allocated ++ PendingMembers.clear(); ++ ++ // This will be allocated by the last member of the aggregate + return true; + } + +Index: lib/Target/ARM/ARMCallingConv.td +=================================================================== +--- lib/Target/ARM/ARMCallingConv.td ++++ lib/Target/ARM/ARMCallingConv.td +@@ -175,7 +175,7 @@ def CC_ARM_AAPCS_VFP : CallingConv<[ + CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, + + // HFAs are passed in a contiguous block of registers, or on the stack +- CCIfConsecutiveRegs<CCCustom<"CC_ARM_AAPCS_Custom_HA">>, ++ CCIfConsecutiveRegs<CCCustom<"CC_ARM_AAPCS_Custom_Aggregate">>, + + CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, + CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, +Index: lib/Target/ARM/ARMISelLowering.cpp +=================================================================== +--- lib/Target/ARM/ARMISelLowering.cpp ++++ lib/Target/ARM/ARMISelLowering.cpp +@@ -11280,7 +11280,9 @@ static bool isHomogeneousAggregate(Type *Ty, HABas + return (Members > 0 && Members <= 4); + } + +-/// \brief Return true if a type is an AAPCS-VFP homogeneous aggregate. ++/// \brief Return true if a type is an AAPCS-VFP homogeneous aggregate or one of ++/// [N x i32] or [N x i64]. This allows front-ends to skip emitting padding when ++/// passing according to AAPCS rules. + bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters( + Type *Ty, CallingConv::ID CallConv, bool isVarArg) const { + if (getEffectiveCallingConv(CallConv, isVarArg) != +@@ -11289,7 +11291,9 @@ bool ARMTargetLowering::functionArgumentNeedsConse + + HABaseType Base = HA_UNKNOWN; + uint64_t Members = 0; +- bool result = isHomogeneousAggregate(Ty, Base, Members); +- DEBUG(dbgs() << "isHA: " << result << " "; Ty->dump()); +- return result; ++ bool IsHA = isHomogeneousAggregate(Ty, Base, Members); ++ DEBUG(dbgs() << "isHA: " << IsHA << " "; Ty->dump()); ++ ++ bool IsIntArray = Ty->isArrayTy() && Ty->getArrayElementType()->isIntegerTy(); ++ return IsHA || IsIntArray; + } +Index: test/CodeGen/ARM/aggregate-padding.ll +=================================================================== +--- test/CodeGen/ARM/aggregate-padding.ll ++++ test/CodeGen/ARM/aggregate-padding.ll +@@ -0,0 +1,101 @@ ++; RUN: llc -mtriple=armv7-linux-gnueabihf %s -o - | FileCheck %s ++ ++; [2 x i64] should be contiguous when split (e.g. we shouldn't try to align all ++; i32 components to 64 bits). Also makes sure i64 based types are properly ++; aligned on the stack. ++define i64 @test_i64_contiguous_on_stack([8 x double], float, i32 %in, [2 x i64] %arg) nounwind { ++; CHECK-LABEL: test_i64_contiguous_on_stack: ++; CHECK-DAG: ldr [[LO0:r[0-9]+]], [sp, #8] ++; CHECK-DAG: ldr [[HI0:r[0-9]+]], [sp, #12] ++; CHECK-DAG: ldr [[LO1:r[0-9]+]], [sp, #16] ++; CHECK-DAG: ldr [[HI1:r[0-9]+]], [sp, #20] ++; CHECK: adds r0, [[LO0]], [[LO1]] ++; CHECK: adc r1, [[HI0]], [[HI1]] ++ ++ %val1 = extractvalue [2 x i64] %arg, 0 ++ %val2 = extractvalue [2 x i64] %arg, 1 ++ %sum = add i64 %val1, %val2 ++ ret i64 %sum ++} ++ ++; [2 x i64] should try to use looks for 4 regs, not 8 (which might happen if the ++; i64 -> i32, i32 split wasn't handled correctly). ++define i64 @test_2xi64_uses_4_regs([8 x double], float, [2 x i64] %arg) nounwind { ++; CHECK-LABEL: test_2xi64_uses_4_regs: ++; CHECK-DAG: mov r0, r2 ++; CHECK-DAG: mov r1, r3 ++ ++ %val = extractvalue [2 x i64] %arg, 1 ++ ret i64 %val ++} ++ ++; An aggregate should be able to split between registers and stack if there is ++; nothing else on the stack. ++define i32 @test_aggregates_split([8 x double], i32, [4 x i32] %arg) nounwind { ++; CHECK-LABEL: test_aggregates_split: ++; CHECK: ldr [[VAL3:r[0-9]+]], [sp] ++; CHECK: add r0, r1, [[VAL3]] ++ ++ %val0 = extractvalue [4 x i32] %arg, 0 ++ %val3 = extractvalue [4 x i32] %arg, 3 ++ %sum = add i32 %val0, %val3 ++ ret i32 %sum ++} ++ ++; If an aggregate has to be moved entirely onto the stack, nothing should be ++; able to use r0-r3 any more. Also checks that [2 x i64] properly aligned when ++; it uses regs. ++define i32 @test_no_int_backfilling([8 x double], float, i32, [2 x i64], i32 %arg) nounwind { ++; CHECK-LABEL: test_no_int_backfilling: ++; CHECK: ldr r0, [sp, #24] ++ ret i32 %arg ++} ++ ++; Even if the argument was successfully allocated as reg block, there should be ++; no backfillig to r1. ++define i32 @test_no_int_backfilling_regsonly(i32, [1 x i64], i32 %arg) { ++; CHECK-LABEL: test_no_int_backfilling_regsonly: ++; CHECK: ldr r0, [sp] ++ ret i32 %arg ++} ++ ++; If an aggregate has to be moved entirely onto the stack, nothing should be ++; able to use r0-r3 any more. ++define float @test_no_float_backfilling([7 x double], [4 x i32], i32, [4 x double], float %arg) nounwind { ++; CHECK-LABEL: test_no_float_backfilling: ++; CHECK: vldr s0, [sp, #40] ++ ret float %arg ++} ++ ++; They're a bit pointless, but types like [N x i8] should work as well. ++define i8 @test_i8_in_regs(i32, [3 x i8] %arg) { ++; CHECK-LABEL: test_i8_in_regs: ++; CHECK: add r0, r1, r3 ++ %val0 = extractvalue [3 x i8] %arg, 0 ++ %val2 = extractvalue [3 x i8] %arg, 2 ++ %sum = add i8 %val0, %val2 ++ ret i8 %sum ++} ++ ++define i16 @test_i16_split(i32, i32, [3 x i16] %arg) { ++; CHECK-LABEL: test_i16_split: ++; CHECK: ldrh [[VAL2:r[0-9]+]], [sp] ++; CHECK: add r0, r2, [[VAL2]] ++ %val0 = extractvalue [3 x i16] %arg, 0 ++ %val2 = extractvalue [3 x i16] %arg, 2 ++ %sum = add i16 %val0, %val2 ++ ret i16 %sum ++} ++ ++; Beware: on the stack each i16 still gets a 32-bit slot, the array is not ++; packed. ++define i16 @test_i16_forced_stack([8 x double], double, i32, i32, [3 x i16] %arg) { ++; CHECK-LABEL: test_i16_forced_stack: ++; CHECK-DAG: ldrh [[VAL0:r[0-9]+]], [sp, #8] ++; CHECK-DAG: ldrh [[VAL2:r[0-9]+]], [sp, #16] ++; CHECK: add r0, [[VAL0]], [[VAL2]] ++ %val0 = extractvalue [3 x i16] %arg, 0 ++ %val2 = extractvalue [3 x i16] %arg, 2 ++ %sum = add i16 %val0, %val2 ++ ret i16 %sum ++} Modified: projects/ifnet/contrib/tzdata/asia ============================================================================== --- projects/ifnet/contrib/tzdata/asia Wed Mar 25 13:57:54 2015 (r280613) +++ projects/ifnet/contrib/tzdata/asia Wed Mar 25 14:05:51 2015 (r280614) @@ -1904,6 +1904,13 @@ Zone Indian/Maldives 4:54:00 - LMT 1880 # was at the start of 2008-03-31 (the day of Steffen Thorsen's report); # this is almost surely wrong. +# From Ganbold Tsagaankhuu (2015-03-10): +# It seems like yesterday Mongolian Government meeting has concluded to use +# daylight saving time in Mongolia.... Starting at 2:00AM of last Saturday of +# March 2015, daylight saving time starts. And 00:00AM of last Saturday of +# September daylight saving time ends. Source: +# http://zasag.mn/news/view/8969 + # Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S Rule Mongol 1983 1984 - Apr 1 0:00 1:00 S Rule Mongol 1983 only - Oct 1 0:00 0 - @@ -1924,6 +1931,8 @@ Rule Mongol 1984 1998 - Sep lastSun 0:00 Rule Mongol 2001 only - Apr lastSat 2:00 1:00 S Rule Mongol 2001 2006 - Sep lastSat 2:00 0 - Rule Mongol 2002 2006 - Mar lastSat 2:00 1:00 S +Rule Mongol 2015 max - Mar lastSat 2:00 1:00 S +Rule Mongol 2015 max - Sep lastSat 0:00 0 - # Zone NAME GMTOFF RULES FORMAT [UNTIL] # Hovd, a.k.a. Chovd, Dund-Us, Dzhargalant, Khovd, Jirgalanta @@ -2342,13 +2351,19 @@ Zone Asia/Karachi 4:28:12 - LMT 1907 # official source...: # http://www.palestinecabinet.gov.ps/ar/Views/ViewDetails.aspx?pid=1252 -# From Paul Eggert (2013-09-24): -# For future dates, guess the last Thursday in March at 24:00 through -# the first Friday on or after September 21 at 00:00. This is consistent with -# the predictions in today's editions of the following URLs, -# which are for Gaza and Hebron respectively: -# http://www.timeanddate.com/worldclock/timezone.html?n=702 -# http://www.timeanddate.com/worldclock/timezone.html?n=2364 +# From Steffen Thorsen (2015-03-03): +# Sources such as http://www.alquds.com/news/article/view/id/548257 +# and http://www.raya.ps/ar/news/890705.html say Palestine areas will +# start DST on 2015-03-28 00:00 which is one day later than expected. +# +# From Paul Eggert (2015-03-03): +# http://www.timeanddate.com/time/change/west-bank/ramallah?year=2014 +# says that the fall 2014 transition was Oct 23 at 24:00. +# For future dates, guess the last Friday in March at 24:00 through +# the first Friday on or after October 21 at 00:00. This is consistent with +# the predictions in today's editions of the following URLs: +# http://www.timeanddate.com/time/change/gaza-strip/gaza +# http://www.timeanddate.com/time/change/west-bank/hebron # Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S Rule EgyptAsia 1957 only - May 10 0:00 1:00 S @@ -2374,9 +2389,11 @@ Rule Palestine 2011 only - Apr 1 0:01 1 Rule Palestine 2011 only - Aug 1 0:00 0 - Rule Palestine 2011 only - Aug 30 0:00 1:00 S Rule Palestine 2011 only - Sep 30 0:00 0 - -Rule Palestine 2012 max - Mar lastThu 24:00 1:00 S +Rule Palestine 2012 2014 - Mar lastThu 24:00 1:00 S Rule Palestine 2012 only - Sep 21 1:00 0 - -Rule Palestine 2013 max - Sep Fri>=21 0:00 0 - +Rule Palestine 2013 only - Sep Fri>=21 0:00 0 - +Rule Palestine 2014 max - Oct Fri>=21 0:00 0 - +Rule Palestine 2015 max - Mar lastFri 24:00 1:00 S # Zone NAME GMTOFF RULES FORMAT [UNTIL] Zone Asia/Gaza 2:17:52 - LMT 1900 Oct Modified: projects/ifnet/contrib/tzdata/australasia ============================================================================== --- projects/ifnet/contrib/tzdata/australasia Wed Mar 25 13:57:54 2015 (r280613) +++ projects/ifnet/contrib/tzdata/australasia Wed Mar 25 14:05:51 2015 (r280614) @@ -373,6 +373,7 @@ Zone Pacific/Guam -14:21:00 - LMT 1844 D 9:39:00 - LMT 1901 # Agana 10:00 - GST 2000 Dec 23 # Guam 10:00 - ChST # Chamorro Standard Time +Link Pacific/Guam Pacific/Saipan # N Mariana Is # Kiribati # Zone NAME GMTOFF RULES FORMAT [UNTIL] @@ -388,12 +389,7 @@ Zone Pacific/Kiritimati -10:29:20 - LMT 14:00 - LINT # N Mariana Is -# Zone NAME GMTOFF RULES FORMAT [UNTIL] -Zone Pacific/Saipan -14:17:00 - LMT 1844 Dec 31 - 9:43:00 - LMT 1901 - 9:00 - MPT 1969 Oct # N Mariana Is Time - 10:00 - MPT 2000 Dec 23 - 10:00 - ChST # Chamorro Standard Time +# See Pacific/Guam. # Marshall Is # Zone NAME GMTOFF RULES FORMAT [UNTIL] @@ -563,6 +559,7 @@ Zone Pacific/Pago_Pago 12:37:12 - LMT 1 -11:00 - NST 1967 Apr # N=Nome -11:00 - BST 1983 Nov 30 # B=Bering -11:00 - SST # S=Samoa +Link Pacific/Pago_Pago Pacific/Midway # in US minor outlying islands # Samoa (formerly and also known as Western Samoa) @@ -744,23 +741,7 @@ Zone Pacific/Funafuti 11:56:52 - LMT 190 # uninhabited # Midway -# -# From Mark Brader (2005-01-23): -# [Fallacies and Fantasies of Air Transport History, by R.E.G. Davies, -# published 1994 by Paladwr Press, McLean, VA, USA; ISBN 0-9626483-5-3] -# reproduced a Pan American Airways timetable from 1936, for their weekly -# "Orient Express" flights between San Francisco and Manila, and connecting -# flights to Chicago and the US East Coast. As it uses some time zone -# designations that I've never seen before:.... -# Fri. 6:30A Lv. HONOLOLU (Pearl Harbor), H.I. H.L.T. Ar. 5:30P Sun. -# " 3:00P Ar. MIDWAY ISLAND . . . . . . . . . M.L.T. Lv. 6:00A " -# -Zone Pacific/Midway -11:49:28 - LMT 1901 - -11:00 - NST 1956 Jun 3 - -11:00 1:00 NDT 1956 Sep 2 - -11:00 - NST 1967 Apr # N=Nome - -11:00 - BST 1983 Nov 30 # B=Bering - -11:00 - SST # S=Samoa +# See Pacific/Pago_Pago. # Palmyra # uninhabited since World War II; was probably like Pacific/Kiritimati Modified: projects/ifnet/contrib/tzdata/europe ============================================================================== --- projects/ifnet/contrib/tzdata/europe Wed Mar 25 13:57:54 2015 (r280613) +++ projects/ifnet/contrib/tzdata/europe Wed Mar 25 14:05:51 2015 (r280614) @@ -2400,7 +2400,7 @@ Zone Europe/Volgograd 2:57:40 - LMT 192 4:00 Russia VOL%sT 1989 Mar 26 2:00s # Volgograd T 3:00 Russia VOL%sT 1991 Mar 31 2:00s 4:00 - VOLT 1992 Mar 29 2:00s - 3:00 Russia MSK 2011 Mar 27 2:00s + 3:00 Russia MSK/MSD 2011 Mar 27 2:00s 4:00 - MSK 2014 Oct 26 2:00s 3:00 - MSK Modified: projects/ifnet/contrib/tzdata/leap-seconds.list ============================================================================== --- projects/ifnet/contrib/tzdata/leap-seconds.list Wed Mar 25 13:57:54 2015 (r280613) +++ projects/ifnet/contrib/tzdata/leap-seconds.list Wed Mar 25 14:05:51 2015 (r280614) @@ -131,10 +131,10 @@ # over the last few minutes of the day. The frequency of the local # clock is decreased (or increased) to realize the positive (or # negative) leap second. This method removes the time step described -# above. Although the long-term behavior of the time scale is correct -# in this case, this method introduces an error during the adjustment -# period both in time and in frequency with respect to the official -# defintion of UTC. +# above. Although the long-term behavior of the time scale is correct +# in this case, this method introduces an error during the adjustment +# period both in time and in frequency with respect to the official +# definition of UTC. # # Questions or comments to: # Judah Levine Modified: projects/ifnet/contrib/tzdata/northamerica ============================================================================== --- projects/ifnet/contrib/tzdata/northamerica Wed Mar 25 13:57:54 2015 (r280613) +++ projects/ifnet/contrib/tzdata/northamerica Wed Mar 25 14:05:51 2015 (r280614) @@ -2312,8 +2312,24 @@ Zone America/Dawson -9:17:40 - LMT 1900 # "...the new time zone will come into effect at two o'clock on the first Sunday # of February, when we will have to advance the clock one hour from its current # time..." -# # Also, the new zone will not use DST. +# +# From Carlos Raúl Perasso (2015-02-02): +# The decree that modifies the Mexican Hour System Law has finally +# been published at the Diario Oficial de la Federación +# http://www.dof.gob.mx/nota_detalle.php?codigo=5380123&fecha=31/01/2015 +# It establishes 5 zones for Mexico: +# 1- Zona Centro (Central Zone): Corresponds to longitude 90 W, +# includes most of Mexico, excluding what's mentioned below. +# 2- Zona Pacífico (Pacific Zone): Longitude 105 W, includes the +# states of Baja California Sur; Chihuahua; Nayarit (excluding Bahía +# de Banderas which lies in Central Zone); Sinaloa and Sonora. +# 3- Zona Noroeste (Northwest Zone): Longitude 120 W, includes the +# state of Baja California. +# 4- Zona Sureste (Southeast Zone): Longitude 75 W, includes the state +# of Quintana Roo. +# 5- The islands, reefs and keys shall take their timezone from the +# longitude they are located at. # Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S Rule Mexico 1939 only - Feb 5 0:00 1:00 D @@ -2508,13 +2524,8 @@ Zone America/Santa_Isabel -7:39:28 - LMT ############################################################################### # Anguilla -# See America/Port_of_Spain. - # Antigua and Barbuda -# Zone NAME GMTOFF RULES FORMAT [UNTIL] -Zone America/Antigua -4:07:12 - LMT 1912 Mar 2 - -5:00 - EST 1951 - -4:00 - AST +# See America/Port_of_Spain. # Bahamas # @@ -2581,10 +2592,7 @@ Zone Atlantic/Bermuda -4:19:18 - LMT 193 -4:00 US A%sT # Cayman Is -# Zone NAME GMTOFF RULES FORMAT [UNTIL] -Zone America/Cayman -5:25:32 - LMT 1890 # Georgetown - -5:07:11 - KMT 1912 Feb # Kingston Mean Time - -5:00 - EST +# See America/Panama. # Costa Rica @@ -3107,6 +3115,7 @@ Zone America/Managua -5:45:08 - LMT 1890 Zone America/Panama -5:18:08 - LMT 1890 -5:19:36 - CMT 1908 Apr 22 # Colón Mean Time -5:00 - EST +Link America/Panama America/Cayman # Puerto Rico # There are too many San Juans elsewhere, so we'll use 'Puerto_Rico'. Modified: projects/ifnet/contrib/tzdata/southamerica ============================================================================== --- projects/ifnet/contrib/tzdata/southamerica Wed Mar 25 13:57:54 2015 (r280613) +++ projects/ifnet/contrib/tzdata/southamerica Wed Mar 25 14:05:51 2015 (r280614) @@ -1206,10 +1206,13 @@ Zone America/Rio_Branco -4:31:12 - LMT 1 # DST Start: first Saturday of September 2014 (Sun 07 Sep 2014 04:00 UTC) # http://www.diariooficial.interior.gob.cl//media/2014/02/19/do-20140219.pdf -# From Juan Correa (2015-01-28): -# ... today the Ministry of Energy announced that Chile will drop DST, will keep -# "summer time" (UTC -3 / UTC -5) all year round.... -# http://www.minenergia.cl/ministerio/noticias/generales/ministerio-de-energia-anuncia.html +# From Eduardo Romero Urra (2015-03-03): +# Today has been published officially that Chile will use the DST time +# permanently until March 25 of 2017 +# http://www.diariooficial.interior.gob.cl/media/2015/03/03/1-large.jpg +# +# From Paul Eggert (2015-03-03): +# For now, assume that the extension will persist indefinitely. # NOTE: ChileAQ rules for Antarctic bases are stored separately in the # 'antarctica' file. @@ -1268,7 +1271,7 @@ Zone America/Santiago -4:42:46 - LMT 189 -3:00 - CLT Zone Pacific/Easter -7:17:44 - LMT 1890 -7:17:28 - EMT 1932 Sep # Easter Mean Time - -7:00 Chile EAS%sT 1982 Mar 13 3:00u # Easter Time + -7:00 Chile EAS%sT 1982 Mar 14 3:00u # Easter Time -6:00 Chile EAS%sT 2015 Apr 26 3:00u -5:00 - EAST # @@ -1603,6 +1606,7 @@ Zone America/Port_of_Spain -4:06:04 - LM # These all agree with Trinidad and Tobago since 1970. Link America/Port_of_Spain America/Anguilla +Link America/Port_of_Spain America/Antigua Link America/Port_of_Spain America/Dominica Link America/Port_of_Spain America/Grenada Link America/Port_of_Spain America/Guadeloupe Modified: projects/ifnet/include/pthread.h ============================================================================== --- projects/ifnet/include/pthread.h Wed Mar 25 13:57:54 2015 (r280613) +++ projects/ifnet/include/pthread.h Wed Mar 25 14:05:51 2015 (r280614) *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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