Date: Sun, 04 Jan 1998 21:39:09 -0800 From: Wayne Scott <wscott@ichips.intel.com> To: "Russell L. Carter" <rcarter@consys.com> Cc: dyson@FreeBSD.ORG, garbanzo@hooked.net (Alex), current@FreeBSD.ORG Subject: Re: Pentium optimizations Message-ID: <199801050539.VAA02628@pdxlx008.pdx.intel.com> In-Reply-To: Your message of "Wed, 17 Dec 1997 08:42:33 MST." <199712171542.IAA09962@dnstoo.consys.com>
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> The out-of-order execution seems to help a lot. Oh, and the P5
> specific asm actually makes the PPro slow down over the C source;
> not good tidings for ye merry old tuners.
>
> }areas of reasonable payoffs, and lots of "obvious" optimizations that
> }end up being neutral.
>
> Yep. I wouldn't worry too much about other people's claims about code
> optimized for Pentium Pro.
>
> Russell
When optimizing for the P6, the main things you should worry about are:
branch prediction
hitting the caches
No unaligned data, and no partials.
For example, for branch prediction, the compile should try to make all
branches you don't take go forward so they don't occupy the BTB.
Code selection does matter, but only is special cases.
=Wayne
Wayne Scott MD6 Architecture - Intel Corp.
wscott@ichips.intel.com Work #: (503) 264-4165
Disclaimer: All views expressed are my own opinions, and not necessarily
those of Intel Corporation.
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