Date: Fri, 3 Jul 2015 07:00:24 +0000 (UTC) From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r285083 - head/sys/mips/atheros Message-ID: <201507030700.t6370Oer015169@repo.freebsd.org>
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Author: adrian Date: Fri Jul 3 07:00:24 2015 New Revision: 285083 URL: https://svnweb.freebsd.org/changeset/base/285083 Log: Oops - fix typo. Modified: head/sys/mips/atheros/qca955xreg.h Modified: head/sys/mips/atheros/qca955xreg.h ============================================================================== --- head/sys/mips/atheros/qca955xreg.h Fri Jul 3 06:15:54 2015 (r285082) +++ head/sys/mips/atheros/qca955xreg.h Fri Jul 3 07:00:24 2015 (r285083) @@ -212,9 +212,9 @@ #define QCA955X_DDR_REG_FLUSH_PCIE (AR71XX_APB_BASE + 0xa8) #define QCA955X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0xac) /* PCIe EP */ -#define QCA955X_DDR_REG_FLUSH_SRC1 (AR71XX_APB_BSAE + 0xb0) +#define QCA955X_DDR_REG_FLUSH_SRC1 (AR71XX_APB_BASE + 0xb0) /* checksum engine */ -#define QCA955X_DDR_REG_FLUSH_SRC2 (AR71XX_APB_BSAE + 0xb2) +#define QCA955X_DDR_REG_FLUSH_SRC2 (AR71XX_APB_BASE + 0xb2) /* PCIe control block - relative to PCI_CTRL_BASE0/PCI_CTRL_BASE1 */
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