Date: Sun, 13 Oct 1996 15:52:17 -0700 From: Thomas Pfenning <thomaspf@microsoft.com> To: "'Peter Wemm'" <peter@spinner.dialix.com>, "'Tonyhain@mirosoft.com'" <Tonyhain@mirosoft.com> Cc: "'mo@UU.NET'" <mo@UU.NET>, "'smp@freebsd.org'" <smp@freebsd.org> Subject: RE: dual-cpu PPRO motherboards... Message-ID: <c=US%a=_%p=msft%l=RED-81-MSG-961013225217Z-46427@mail4.microsoft.com>
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The Tomcat is indeed a HX board. Is interrupt steering supported by the Natoma? What you describe actually happens when we boot the box with NT4.0. While the BIOS assigns 255 (no assignment) all devices are mapped to interrupts as soon as NT takes control. I can't wait to see the SMP changes make it on a boot floppy because otherwise I have to put the disk into a different machine to bootstrap. Cheers Thomas >-----Original Message----- >From: Peter Wemm [SMTP:peter@spinner.DIALix.COM] >Sent: Sunday, October 13, 1996 3:43 PM >To: Thomas Pfenning >Cc: 'mo@UU.NET'; 'smp@freebsd.org' >Subject: Re: dual-cpu PPRO motherboards... > >Thomas Pfenning wrote: >> Hi Mike, >> >> we just received a Tomcat 2 with hardware revision 4, which is just a >> dual Pentium board but shows a trend. Tyan decided in their great wisdom >> that people will always want the IDE interrupts and hardwired them to 14 >> and 15. This combined with the Award BIOS (same functionality as with >> the Natoma) prevents our brand new machine from even booting the floppy. >> >> The Award Bios does not allow you to manually assign a fixed interrupt >> to a PCI slot. In our configuration both the automatic and the manual >> mode of the BIOS fail which is only a partial surprise since we need >> more interrupts than left by subtracting 14 and 15. > >Hmm, I read somewhere that the Triton-II HX chipset "doesn't support >interrupt steering", perhaps this is what they meant? What is the Tomcat >2's chipset? > >The other "interesting" news is that the mpspec1.4 compliant motherboards >are supposed to have the PCI interrupts wired to different APIC interrupt >inputs. The IO APIC chipset that goes with the T2-HX pciset and friends >has 24 interrupt inputs, of which the first 16 typically go to the ISA >bus, the next 4 go to the PCI bus, and the spares are used for other >things like SMI and so on. > >With the work that Steve's been doing on the IO APIC stuff to get it >running in full symmetric IO mode (rather than virtual wire), this >restriction should become only a bootstrap problem. Once the system is >running fully symmetric, you have a total of 20 interrupts available. The >IDE interrupts will disappear from irq-14 and 15 once it's switched to >symmetric mode, so if you have smart cards in there that have programmable >irq's, those will be available for assignment shortly after boot. Once >the pci code has been "taught" about interrupts that change after bootup >and when to ignore the irq mapping registers, it should be nice. There's >a lot of hard coded stuff at the moment that suits Steve's particular >machine though, for some strange reason. ;-) > >Cheers, >-Peter > >home | help
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