Date: Wed, 30 Jul 1997 16:36:30 -0400 (EDT) From: Andrew Gallatin <gallatin@CS.Duke.EDU> To: Stefan Esser <se@freebsd.org> Cc: freebsd-current@freebsd.org Subject: Re: code talks: announcing EIDE bus master patches Message-ID: <199707302036.QAA23330@hurricane.cs.duke.edu> In-Reply-To: <19970730220038.02422@mi.uni-koeln.de> References: <19970729210723.18104@mi.uni-koeln.de> <199707291949.VAA00271@sos.freebsd.dk> <19970729221036.52544@mi.uni-koeln.de> <199707301924.PAA08936@hurricane.cs.duke.edu> <19970730220038.02422@mi.uni-koeln.de>
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Stefan Esser writes:
> On Jul 30, Andrew Gallatin <gallatin@CS.Duke.EDU> wrote:
> > Speaking of PIO vs. DMA, an interesting data point is the bandwidth
> > differences between PIO & DMA.
> >
> > For example, on a 200Mhz P. Pro (Asus XP6NP5, Intel 82440FX chipset)
> > we can use PIO to move an 8k chunks of memory to a PCI device(*) at a
> > rate of 29.1 MB/sec, but using PIO for reads gives us bandwidth of
> > only 8.1MB/sec. Other platforms (Intel Triton @ 13MB/sec) show
> > similar results. However, using DMA we see b/w of 114.4MB/sec (host
> > -> PCI device) and 121.5 MB/sec (PCI -> host memory).
>
> Is this PIO to an I/O port, or to a memory mapped port ?
It's memory mapped PCI memory.
> But in any case: In order to use PCI burst transfers, you
> have to write to sequential memory addresses, e.g. to some
> double-mapped SRAM buffer.
Double-mapped? What does that mean?
> PCI is slow, if you can't take advantage of burst transfers!
>
> > So.. if IDE disks can really supply data at > 8MB/sec, you may
> > actually be running into a b/w limitation of PIO.
>
> If you assume 8 PCI clocks for a non-burst transfer, the
> limit comes out as 16MB/s. (The minimum is 4 clocks for
> such a transfer, but don't assume your chip-set does
> support that :)
>
> > (*) PCI device == a Myrinet M2F-PCI32 card. This is a programmable
> > gigabit networking card. It has a 256k bank of SRAM on the card, and
> > is very good for doing things like measuring PCI b/w. The tests were
> > done from user space operating on mmap'ed device memory & a kernel
> > allocated chunk of RAM to do DMA xfers to/from. It also runs IP
> > traffic at better than 300Mb/sec.
>
> This was a memory mapped device buffer ?
Yes.
> That's *very* different from an I/O port, and you should be able
> to copy data to that SRAM at a much higher rate than 8 or 13MB/s!
Right. The Natoma is using burst transfers for PIO writes and getting
nearly 30MB/sec. Its apparently not bursting the reads, and is
getting only 8MB/sec. How do you get an Intel to burst reads? I
didn't think they could support multiple outstanding reads. I know
that alphas do, and there are apparently tricks you can use to make an
alpha burst reads & get 50MB/sec bandwidth, but I wasn't aware of
Intels that could get better than 15MB/sec for PIO reads.
I'm getting most of my information from emperical results obtained
with our P6's and Alphas using Myrinet cards, plus the DEC PCI Pamette
paper ("Systems Performance Measurement on PCI Pamette", Laurent Moll,
Mark Shand, Fccm97, ftp://pam.devinci.fr/pub/pamette/fccm97.ps.gz).
>
> Regards, STefan
Drew
------------------------------------------------------------------------------
Andrew Gallatin http://www.cs.duke.edu/~gallatin
Duke University Email: gallatin@cs.duke.edu
Department of Computer Science Phone: (919) 660-6590
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