Date: Tue, 23 Sep 2008 15:58:38 +0900 From: "G .Otsuji" <annona2@gmail.com> To: "fluffles.net" <bsd@fluffles.net> Cc: "G.Otsuji" <annona2@gmail.com>, FreeBSD Current <freebsd-current@freebsd.org> Subject: Re: AMD Family 10h cpufreq driver Message-ID: <200809230658.m8N6wcxM002487@softbank219001162114.bbtec.net> In-Reply-To: <48D85FC0.5050807@fluffles.net> References: <200809070036.m870a3NC001532@softbank219001162114.bbtec.net> <48D72F0E.7040501@fluffles.net> <200809222333.m8MNXiuS064364@softbank219001162114.bbtec.net> <48D85FC0.5050807@fluffles.net>
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Hi Veronica, I haven't read yet much so mail again. > I want to mention i'm using amd64, do your intructions account for that? > Because i see a i386 directory, although if i see some stuff about amd64 > in the makefile that suggests it also uses that directory. Just want a > confirmation from you that this is not a problem. Yes! It's not a problem. > From: http://www.xbitlabs.com/articles/cpu/display/amd-phenom_3.html >=20 > Cool=E2=80=99nQuiet technology in Phenom processors got to a completely n= ew > level, too. Now they call it Cool=E2=80=99n=E2=80=99Quiet 2.0. It allows = to > independently adjust the power consumption and frequency of all four > processor cores and memory controller. Yes,too!. but ,FreeBSD has only one oid dev.cpu.0.freq_levels/dev.cpu.0.fre= q. I think it is possible that dev.cpu.1.freq=3D1000 and dev.cpu.2.freq=3D1200= or so. But freebsd is not yet enabled this feature. > Moreover, Phenom also supports C1E state that takes place for the > processor after a few milliseconds of idling. In this case the CPU not > only drops down its clock speed, but also reduces the HyperTransport and > system bus power consumption. >=20 > Another new and pretty interesting feature of the Cool=E2=80=99n=E2=80=99= Quiet 2.0 > technology is the ability of the CPU voltage regulator to receive data > on the current power-saving CPU mode. Theoretically, it allows adjusting > the voltage regulator circuitry parameters interactively depending on > the processor operational conditions. I believe that mainboard > developers will be able to implement corresponding algorithms in their > solutions. Yes.the voltage is dropping as the cpu clock-downs with pstate modules. boot -v will writes this message if goes well. > AMD CPUs with C1E support are currently excluded from high resolution > timers and NOHZ support. The reason is that C1E is a BIOS controlled > C3 power state which switches off TSC and the local APIC timer. The > ACPI C-State control manages the TSC/local APIC timer wreckage, but > this does not include the C1 based ("halt" instruction) C1E mode. The > BIOS/SMM controlled C1E state works on most systems even without > enabling ACPI C-State control. ACPI is not my knowing area, so rewriting is welcome! Cheers, G. Otsuji<annona2@gmail.com>
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