Date: Sun, 20 Mar 2011 08:47:59 +0000 (UTC) From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r219793 - head/sys/dev/ath/ath_hal/ar5416 Message-ID: <201103200847.p2K8lxWX049989@svn.freebsd.org>
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Author: adrian Date: Sun Mar 20 08:47:59 2011 New Revision: 219793 URL: http://svn.freebsd.org/changeset/base/219793 Log: * Remove a not-needed check in the AR5416+ case * Restore the chip default of the DCU backoff threshold to 0x2, mirroring what ath9k does. Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c Sun Mar 20 08:42:56 2011 (r219792) +++ head/sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c Sun Mar 20 08:47:59 2011 (r219793) @@ -919,12 +919,12 @@ ar5416ResetTxQueue(struct ath_hal *ah, u /* NB: always enable DCU to wait for next fragment from QCU */ dmisc = AR_D_MISC_FRAG_WAIT_EN; -#ifdef AH_SUPPORT_5311 - if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) { - /* Configure DCU to use the global sequence count */ - dmisc |= AR5311_D_MISC_SEQ_NUM_CONTROL; - } -#endif + /* + * The chip reset default is to use a DCU backoff threshold of 0x2. + * Restore this when programming the DCU MISC register. + */ + dmisc |= 0x2; + /* multiqueue support */ if (qi->tqi_cbrPeriod) { OS_REG_WRITE(ah, AR_QCBRCFG(q),
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