Date: Wed, 16 Jan 2002 08:54:47 +0100 (CET) From: Michal Mertl <mime@traveller.cz> To: John Baldwin <jhb@FreeBSD.ORG> Cc: Peter Jeremy <peter.jeremy@alcatel.com.au>, <arch@FreeBSD.ORG>, Thomas Hurst <tom.hurst@clara.net>, "James E. Housley" <jeh@FreeBSD.ORG>, Bosko Milekic <bmilekic@technokratis.com>, Terry Lambert <tlambert2@mindspring.com> Subject: Re: 64 bit counters again Message-ID: <Pine.BSF.4.41.0201160843480.96117-100000@prg.traveller.cz> In-Reply-To: <XFMail.020115172137.jhb@FreeBSD.org>
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On Tue, 15 Jan 2002, John Baldwin wrote: > > On 16-Jan-02 Peter Jeremy wrote: > > For the read case, the reader uses something like: > > > > loop: movl 4(mem),%edx > > movl (mem),%eax > > cmpl 4(mem),%edx > > jnz loop > > > > If an interrupt updates the MSW then you take another pass around the > > loop, otherwise you always read the correct value. > > > > For the SMP case, you either need to use locks or you need to use > > per-CPU counters. (And the per-CPU counters can be read by another > > CPU using the above trick). > > Well, SMP on Pentium's maybe, but not on Alpha, sparc64, or ia64, all of which > support OOE and looser memory models than x86, meaning that you really need > locks unless you are going to have 386-specific code all over the place. I > suppose you can wrap it behind an MI API but that seems like a lot of work for > fairly small gain that can end up making the code uglier. > This ugly hack is supposed to be required only on 32 bit platforms. For me it's i386 (anything else with >0.1% user base?). On 64 bit platforms you just use native operand size. The code, which is present in the kernel now is most probably broken (at least on i386 compiler generates RMW). If we use something like what I proposed, we can fix it easily. At least I identified lots of places (not that it was difficult to do) where network counters are updated with possibly unsafe operation. -- Michal Mertl mime@traveller.cz To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-arch" in the body of the message
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