Date: Sun, 5 Nov 2017 17:14:44 +0000 (UTC) From: Michal Meloun <mmel@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r325439 - head/sys/arm/arm Message-ID: <201711051714.vA5HEi7I074707@repo.freebsd.org>
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Author: mmel Date: Sun Nov 5 17:14:44 2017 New Revision: 325439 URL: https://svnweb.freebsd.org/changeset/base/325439 Log: Remove support for ARMv6/v7 platform from elf_trampoline. The elf_trampoline.c is not connected to build for ARMv6/v7 for long time and it uses outdated low level cpu functions. This blocks forthcoming cleanup of ARM code. MFC after: 3 weeks Modified: head/sys/arm/arm/elf_trampoline.c Modified: head/sys/arm/arm/elf_trampoline.c ============================================================================== --- head/sys/arm/arm/elf_trampoline.c Sun Nov 5 16:52:54 2017 (r325438) +++ head/sys/arm/arm/elf_trampoline.c Sun Nov 5 17:14:44 2017 (r325439) @@ -41,6 +41,9 @@ __FBSDID("$FreeBSD$"); #include <machine/armreg.h> #include <machine/cpu.h> +#if __ARM_ARCH >= 6 +#error "elf_trampline is not supported on ARMv6/v7 platforms" +#endif extern char kernel_start[]; extern char kernel_end[]; @@ -51,8 +54,6 @@ void __start(void); void __startC(unsigned r0, unsigned r1, unsigned r2, unsigned r3); extern unsigned int cpu_ident(void); -extern void armv6_idcache_wbinv_all(void); -extern void armv7_idcache_wbinv_all(void); extern void do_call(void *, void *, void *, int); #define GZ_HEAD 0xa @@ -66,36 +67,23 @@ extern void fa526_idcache_wbinv_all(void); #elif defined(CPU_ARM9E) #define cpu_idcache_wbinv_all armv5_ec_idcache_wbinv_all extern void armv5_ec_idcache_wbinv_all(void); -#elif defined(CPU_ARM1176) -#define cpu_idcache_wbinv_all armv6_idcache_wbinv_all #elif defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) #define cpu_idcache_wbinv_all xscale_cache_purgeID extern void xscale_cache_purgeID(void); #elif defined(CPU_XSCALE_81342) #define cpu_idcache_wbinv_all xscalec3_cache_purgeID extern void xscalec3_cache_purgeID(void); -#elif defined(CPU_MV_PJ4B) -#if !defined(SOC_MV_ARMADAXP) -#define cpu_idcache_wbinv_all armv6_idcache_wbinv_all -extern void armv6_idcache_wbinv_all(void); -#else -#define cpu_idcache_wbinv_all() armadaxp_idcache_wbinv_all #endif -#endif /* CPU_MV_PJ4B */ #ifdef CPU_XSCALE_81342 #define cpu_l2cache_wbinv_all xscalec3_l2cache_purge extern void xscalec3_l2cache_purge(void); #elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) #define cpu_l2cache_wbinv_all sheeva_l2cache_wbinv_all extern void sheeva_l2cache_wbinv_all(void); -#elif defined(CPU_CORTEXA8) || defined(CPU_CORTEXA_MP) || defined(CPU_KRAIT) -#define cpu_idcache_wbinv_all armv7_idcache_wbinv_all -#define cpu_l2cache_wbinv_all() #else #define cpu_l2cache_wbinv_all() #endif -static void armadaxp_idcache_wbinv_all(void); int arm_picache_size; int arm_picache_line_size; @@ -389,18 +377,6 @@ arm9_setup(void) arm9_dcache_index_max = 0U - arm9_dcache_index_inc; } -static void -armadaxp_idcache_wbinv_all(void) -{ - uint32_t feat; - - __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (feat)); - if (feat & ARM_PFR0_THUMBEE_MASK) - armv7_idcache_wbinv_all(); - else - armv6_idcache_wbinv_all(); - -} #ifdef KZIP static unsigned char *orig_input, *i_input, *i_output;
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