Date: Sun, 30 Nov 2008 00:11:48 +0000 (UTC) From: Alexander Motin <mav@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r185461 - head/sys/i386/i386 Message-ID: <200811300011.mAU0Bmw6066360@svn.freebsd.org>
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Author: mav Date: Sun Nov 30 00:11:48 2008 New Revision: 185461 URL: http://svn.freebsd.org/changeset/base/185461 Log: According to "Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2", CPUs with family 0x6 and model above or 0xE and CPUs with family 0xF and model above or 0x3 have invariant TSC. Modified: head/sys/i386/i386/identcpu.c Modified: head/sys/i386/i386/identcpu.c ============================================================================== --- head/sys/i386/i386/identcpu.c Sun Nov 30 00:10:55 2008 (r185460) +++ head/sys/i386/i386/identcpu.c Sun Nov 30 00:11:48 2008 (r185461) @@ -872,7 +872,11 @@ printcpuinfo(void) tsc_is_invariant = 1; break; case CPU_VENDOR_INTEL: - if (amd_pminfo & AMDPM_TSC_INVARIANT) + if ((amd_pminfo & AMDPM_TSC_INVARIANT) || + (I386_CPU_FAMILY(cpu_id) == 0x6 && + I386_CPU_MODEL(cpu_id) >= 0xe) || + (I386_CPU_FAMILY(cpu_id) == 0xf && + I386_CPU_MODEL(cpu_id) >= 0x3)) tsc_is_invariant = 1; break; }
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