Date: Mon, 20 Jun 2011 19:06:40 +1000 From: Peter Jeremy <peterjeremy@acm.org> To: Bruce Evans <brde@optusnet.com.au> Cc: svn-src-head@FreeBSD.org, svn-src-all@FreeBSD.org, src-committers@FreeBSD.org Subject: Re: svn commit: r222866 - head/sys/x86/x86 Message-ID: <20110620090640.GA64900@server.vk2pj.dyndns.org> In-Reply-To: <20110618210815.W889@besplex.bde.org> References: <201106081938.p58JcWuB044252@svn.freebsd.org> <20110609055112.P2870@besplex.bde.org> <201106081913.09272.jkim@FreeBSD.org> <20110618210815.W889@besplex.bde.org>
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--k1lZvvs/B4yU6o8G Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On 2011-Jun-18 22:05:06 +1000, Bruce Evans <brde@optusnet.com.au> wrote: >My clock measurement program (mostly an old program by Wollman) shows >the following histogram of times for a non-invariant TSC timecounter >on a 2GHz UP system: > >% min 273, max 265102, mean 273.998217, std 79.069534 >% 1th: 273 (1727219 observations) >% 2th: 274 (265607 observations) >% 3th: 275 (6984 observations) >% 4th: 280 (11 observations) >% 5th: 290 (8 observations) > >The variance is small, and differences of a single nS can be seen clearly. Unfortunately, Intel broke this in their P-state invariant TSC implementation. Rather than incrementing the TSC by one at the CPU core frequency, they increment by the core multiplier at the FSB frequency. This gives a result like the following on my Atom N270: delta samples 24 49637124 36 50312540 48 44658 60 77 This makes it virtually impossible to measure short periods. Luckily, AMD seem to have gotten this right. --=20 Peter Jeremy --k1lZvvs/B4yU6o8G Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.17 (FreeBSD) iEYEARECAAYFAk3/DaAACgkQ/opHv/APuIdI0wCgij6nEhp+ektNaMC7IsxhSFdI skwAoJPNjU5v015VsBvQx07kGtOnw9dI =Ehiz -----END PGP SIGNATURE----- --k1lZvvs/B4yU6o8G--
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