Date: Thu, 5 Aug 2010 04:59:54 +0000 (UTC) From: Neel Natu <neel@FreeBSD.org> To: cvs-src-old@freebsd.org Subject: cvs commit: src/sys/mips/mips tick.c src/sys/mips/sibyte sb_machdep.c Message-ID: <201008050500.o755031e023897@repoman.freebsd.org>
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neel 2010-08-05 04:59:54 UTC
FreeBSD src repository
Modified files:
sys/mips/mips tick.c
sys/mips/sibyte sb_machdep.c
Log:
SVN rev 210854 on 2010-08-05 04:59:54Z by neel
Fix a race between clock_intr() and tick_ticker() when updating
'counter_upper' and 'counter_lower_last'. The race exists because
interrupts are enabled even though tick_ticker() executes in a
critical section.
Fix a bug in clock_intr() in how it updates the cached values of
'counter_upper' and 'counter_lower_last'. They are updated only
when the COUNT register rolls over. More interestingly it will *never*
update the cached values if 'counter_lower_last' happens to be zero.
Get rid of superfluous critical section in clock_intr(). There is no
reason to do this because clock_intr() executes in hard interrupt
context.
Switch back to using 'tick_ticker()' as the cpu ticker for Sibyte.
Reviewed by: jmallett, mav
Revision Changes Path
1.17 +29 -17 src/sys/mips/mips/tick.c
1.13 +0 -2 src/sys/mips/sibyte/sb_machdep.c
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