Date: Tue, 1 Jan 2013 16:59:15 +1300 From: Andrew Turner <andrew@fubar.geek.nz> To: Oleksandr Tymoshenko <gonzo@freebsd.org> Cc: svn-src-head@freebsd.org, svn-src-all@freebsd.org, src-committers@freebsd.org Subject: Re: svn commit: r244914 - in head/sys/arm: arm include ti/omap4 Message-ID: <20130101165915.1f903645@fubar.geek.nz> In-Reply-To: <50E20F2B.7080704@freebsd.org> References: <201212312119.qBVLJi3V009555@svn.freebsd.org> <20130101105353.14492943@fubar.geek.nz> <50E20F2B.7080704@freebsd.org>
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On Mon, 31 Dec 2012 14:18:19 -0800
Oleksandr Tymoshenko <gonzo@freebsd.org> wrote:
> On 12/31/2012 1:53 PM, Andrew Turner wrote:
> > On Mon, 31 Dec 2012 21:19:44 +0000 (UTC)
> > Oleksandr Tymoshenko <gonzo@FreeBSD.org> wrote:
> >> Modified: head/sys/arm/arm/pl310.c
> >> ==============================================================================
> >> --- head/sys/arm/arm/pl310.c Mon Dec 31 21:09:39 2012
> >> (r244913) +++ head/sys/arm/arm/pl310.c Mon Dec 31 21:19:44
> > ...
> >> @@ -157,29 +131,46 @@ pl310_wait_background_op(uint32_t off, u
> >> static __inline void
> >> pl310_cache_sync(void)
> >> {
> >> - pl310_write4(PL310_CACHE_SYNC, 0);
> >> + if ((pl310_softc == NULL) || !pl310_softc->sc_enabled)
> >> + return;
> >> +
> >> +#ifdef PL310_ERRATA_753970
> >> + /* Write uncached PL310 register */
> >> + pl310_write4(pl310_softc, 0x740, 0xffffffff);
> >> +#else
> >> + pl310_write4(pl310_softc, PL310_CACHE_SYNC, 0xffffffff);
> >> +#endif
> >> }
> > How hard would it be to detect if we need this errata at boot? From
> > the errata document it appears to only be present in the r3p0
> > revision of the controller. We can then do something like:
> >
> > #ifdef PL310_ERRATA_753970
> > if (errata_753970)
> > pl310_write4(pl310_softc, 0x740, 0xffffffff);
> > else
> > #endif
> > pl310_write4(pl310_softc, PL310_CACHE_SYNC, 0xffffffff);
> >
> >
>
>
> I think we can use RTL release field of Cache ID register to
> determine actual hardware release
> and act accordingly.
>
>
Yes, that appears to be correct, I have committed the known values of
the RTL release field, from the ARM documentation, in r244919. I can
have a look at detecting which cache controller we are on and adjust
our behaviour accordingly but won't have any hardware to test with
until the end of the week.
Andrew
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