Date: Thu, 2 Jan 1997 02:46:28 +0100 (MET) From: Luigi Rizzo <luigi@labinfo.iet.unipi.it> To: msmith@atrad.adelaide.edu.au (Michael Smith) Cc: hmmm@alaska.net, hackers@FreeBSD.ORG Subject: Re: Ints (fwd) Message-ID: <199701020146.CAA00972@labinfo.iet.unipi.it> In-Reply-To: <199701020100.LAA14579@genesis.atrad.adelaide.edu.au> from "Michael Smith" at Jan 2, 97 11:30:35 am
next in thread | previous in thread | raw e-mail | index | archive | help
> hmmm stands accused of saying: > > > > Wait a second guys.... The interrupt lines on the ISA bus are > > open-collector, which means that it is possible to OR-TIE them ... > > ... only ISA interrupt lines aren't open-collector. The RC time > constant implicit in OC circuits (there is a tradeoff between the > risetime and the power dissipation in the driving circuit) is > unacceptable for anything other than the slowest logic. > > Work it out; 5V / 24mA (LSTTL sink limit) = ~200R. Assuming 50pf of > parasitic capacitance (not unreasonable), you get RC = 10usec. Not so > good. (220R is actually the accepted value for LSTTL and compatible > families, witness the 220/330R resistor pairing in passive SCSI > terminators.) of course all this reasoning breaks since 50pf = 50e-12 F so RC is 10 nanoseconds... :) > Just about every other multi-card bus ever invented uses daisy-chained > interrupts or slot interrupts or some other manifestation of a sensible > scheme. But not ISA. YOU CANNOT SHARE INTERRUPTS SAFELY ON ISA. true, but that's because of edge triggered lines as you say later. Were they level sensitive, there would be no problem in sharing them. Luigi
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?199701020146.CAA00972>