Date: Sun, 26 Oct 2014 04:08:34 +0000 (UTC) From: Ian Lepore <ian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r273677 - stable/10/sys/dev/uart Message-ID: <201410260408.s9Q48Yt1039685@svn.freebsd.org>
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Author: ian Date: Sun Oct 26 04:08:34 2014 New Revision: 273677 URL: https://svnweb.freebsd.org/changeset/base/273677 Log: MFC r272334, r273004: Return the actual baud rate programmed in the hardware rather than 115200. This allows the "3wire" entry in /etc/ttys (with no speed specified) to work. Use the FIFOs in the imx5/imx6 uart hardware instead of interrupting on each byte sent or received. Modified: stable/10/sys/dev/uart/uart_dev_imx.c Directory Properties: stable/10/ (props changed) Modified: stable/10/sys/dev/uart/uart_dev_imx.c ============================================================================== --- stable/10/sys/dev/uart/uart_dev_imx.c Sun Oct 26 04:06:29 2014 (r273676) +++ stable/10/sys/dev/uart/uart_dev_imx.c Sun Oct 26 04:08:34 2014 (r273677) @@ -49,6 +49,17 @@ __FBSDID("$FreeBSD$"); #include <arm/freescale/imx/imx_ccmvar.h> /* + * The hardare FIFOs are 32 bytes. We want an interrupt when there are 24 bytes + * available to read or space for 24 more bytes to write. While 8 bytes of + * slack before over/underrun might seem excessive, the hardware can run at + * 5mbps, which means 2uS per char, so at full speed 8 bytes provides only 16uS + * to get into the interrupt handler and service the fifo. + */ +#define IMX_FIFOSZ 32 +#define IMX_RXFIFO_LEVEL 24 +#define IMX_TXFIFO_LEVEL 24 + +/* * Low-level UART interface. */ static int imx_uart_probe(struct uart_bas *bas); @@ -90,6 +101,45 @@ imx_uart_probe(struct uart_bas *bas) return (0); } +static u_int +imx_uart_getbaud(struct uart_bas *bas) +{ + uint32_t rate, ubir, ubmr; + u_int baud, blo, bhi, i; + static const u_int predivs[] = {6, 5, 4, 3, 2, 1, 7, 1}; + static const u_int std_rates[] = { + 9600, 14400, 19200, 38400, 57600, 115200, 230400, 460800, 921600 + }; + + /* + * Get the baud rate the hardware is programmed for, then search the + * table of standard baud rates for a number that's within 3% of the + * actual rate the hardware is programmed for. It's more comforting to + * see that your console is running at 115200 than 114942. Note that + * here we cannot make a simplifying assumption that the predivider and + * numerator are 1 (like we do when setting the baud rate), because we + * don't know what u-boot might have set up. + */ + i = (GETREG(bas, REG(UFCR)) & IMXUART_UFCR_RFDIV_MASK) >> + IMXUART_UFCR_RFDIV_SHIFT; + rate = imx_ccm_uart_hz() / predivs[i]; + ubir = GETREG(bas, REG(UBIR)) + 1; + ubmr = GETREG(bas, REG(UBMR)) + 1; + baud = ((rate / 16 ) * ubir) / ubmr; + + blo = (baud * 100) / 103; + bhi = (baud * 100) / 97; + for (i = 0; i < nitems(std_rates); i++) { + rate = std_rates[i]; + if (rate >= blo && rate <= bhi) { + baud = rate; + break; + } + } + + return (baud); +} + static void imx_uart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, int parity) @@ -148,6 +198,17 @@ imx_uart_init(struct uart_bas *bas, int SETREG(bas, REG(UBIR), 15); SETREG(bas, REG(UBMR), (baseclk / baudrate) - 1); } + + /* + * Program the tx lowater and rx hiwater levels at which fifo-service + * interrupts are signaled. The tx value is interpetted as "when there + * are only this many bytes remaining" (not "this many free"). + */ + reg = GETREG(bas, REG(UFCR)); + reg &= ~(IMXUART_UFCR_TXTL_MASK | IMXUART_UFCR_RXTL_MASK); + reg |= (IMX_FIFOSZ - IMX_TXFIFO_LEVEL) << IMXUART_UFCR_TXTL_SHIFT; + reg |= IMX_RXFIFO_LEVEL << IMXUART_UFCR_RXTL_SHIFT; + SETREG(bas, REG(UFCR), reg); } static void @@ -160,7 +221,7 @@ static void imx_uart_putc(struct uart_bas *bas, int c) { - while (!(IS(bas, USR2, TXFE))) + while (!(IS(bas, USR1, TRDY))) ; SETREG(bas, REG(UTXD), c); } @@ -263,11 +324,15 @@ imx_uart_bus_attach(struct uart_softc *s (void)imx_uart_bus_getsig(sc); - ENA(bas, UCR4, DREN); - DIS(bas, UCR1, RRDYEN); + /* Clear all pending interrupts. */ + SETREG(bas, REG(USR1), 0xffff); + SETREG(bas, REG(USR2), 0xffff); + + DIS(bas, UCR4, DREN); + ENA(bas, UCR1, RRDYEN); DIS(bas, UCR1, IDEN); DIS(bas, UCR3, RXDSEN); - DIS(bas, UCR2, ATEN); + ENA(bas, UCR2, ATEN); DIS(bas, UCR1, TXMPTYEN); DIS(bas, UCR1, TRDYEN); DIS(bas, UCR4, TCEN); @@ -291,9 +356,6 @@ imx_uart_bus_attach(struct uart_softc *s ENA(bas, UCR2, IRTS); ENA(bas, UCR3, RXDMUXSEL); - /* ACK all interrupts */ - SETREG(bas, REG(USR1), 0xffff); - SETREG(bas, REG(USR2), 0xffff); return (0); } @@ -348,8 +410,7 @@ imx_uart_bus_ioctl(struct uart_softc *sc /* TODO */ break; case UART_IOCTL_BAUD: - /* TODO */ - *(int*)data = 115200; + *(u_int*)data = imx_uart_getbaud(bas); break; default: error = EINVAL; @@ -366,7 +427,7 @@ imx_uart_bus_ipend(struct uart_softc *sc struct uart_bas *bas; int ipend; uint32_t usr1, usr2; - uint32_t ucr1, ucr4; + uint32_t ucr1, ucr2, ucr4; bas = &sc->sc_bas; ipend = 0; @@ -381,18 +442,28 @@ imx_uart_bus_ipend(struct uart_softc *sc SETREG(bas, REG(USR2), usr2); ucr1 = GETREG(bas, REG(UCR1)); + ucr2 = GETREG(bas, REG(UCR2)); ucr4 = GETREG(bas, REG(UCR4)); - if ((usr2 & FLD(USR2, TXFE)) && (ucr1 & FLD(UCR1, TXMPTYEN))) { - DIS(bas, UCR1, TXMPTYEN); - /* Continue TXing */ + /* If we have reached tx low-water, we can tx some more now. */ + if ((usr1 & FLD(USR1, TRDY)) && (ucr1 & FLD(UCR1, TRDYEN))) { + DIS(bas, UCR1, TRDYEN); ipend |= SER_INT_TXIDLE; } - if ((usr2 & FLD(USR2, RDR)) && (ucr4 & FLD(UCR4, DREN))) { - DIS(bas, UCR4, DREN); - /* Wow, new char on input */ + + /* + * If we have reached the rx high-water, or if there are bytes in the rx + * fifo and no new data has arrived for 8 character periods (aging + * timer), we have input data to process. + */ + if (((usr1 & FLD(USR1, RRDY)) && (ucr1 & FLD(UCR1, RRDYEN))) || + ((usr1 & FLD(USR1, AGTIM)) && (ucr2 & FLD(UCR2, ATEN)))) { + DIS(bas, UCR1, RRDYEN); + DIS(bas, UCR2, ATEN); ipend |= SER_INT_RXREADY; } + + /* A break can come in at any time, it never gets disabled. */ if ((usr2 & FLD(USR2, BRCD)) && (ucr4 & FLD(UCR4, BKEN))) ipend |= SER_INT_BREAK; @@ -421,8 +492,14 @@ imx_uart_bus_probe(struct uart_softc *sc if (error) return (error); - sc->sc_rxfifosz = 1; - sc->sc_txfifosz = 1; + /* + * On input we can read up to the full fifo size at once. On output, we + * want to write only as much as the programmed tx low water level, + * because that's all we can be certain we have room for in the fifo + * when we get a tx-ready interrupt. + */ + sc->sc_rxfifosz = IMX_FIFOSZ; + sc->sc_txfifosz = IMX_TXFIFO_LEVEL; device_set_desc(sc->sc_dev, "Freescale i.MX UART"); return (0); @@ -437,20 +514,20 @@ imx_uart_bus_receive(struct uart_softc * bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); - /* Read while we have anything in FIFO */ + /* + * Empty the rx fifo. We get the RRDY interrupt when IMX_RXFIFO_LEVEL + * (the rx high-water level) is reached, but we set sc_rxfifosz to the + * full hardware fifo size, so we can safely process however much is + * there, not just the highwater size. + */ while (IS(bas, USR2, RDR)) { if (uart_rx_full(sc)) { /* No space left in input buffer */ sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; break; } - out = 0; xc = GETREG(bas, REG(URXD)); - - /* We have valid char */ - if (xc & FLD(URXD, CHARRDY)) - out = xc & 0x000000ff; - + out = xc & 0x000000ff; if (xc & FLD(URXD, FRMERR)) out |= UART_STAT_FRAMERR; if (xc & FLD(URXD, PRERR)) @@ -462,8 +539,8 @@ imx_uart_bus_receive(struct uart_softc * uart_rx_put(sc, out); } - /* Reenable Data Ready interrupt */ - ENA(bas, UCR4, DREN); + ENA(bas, UCR1, RRDYEN); + ENA(bas, UCR2, ATEN); uart_unlock(sc->sc_hwmtx); return (0); @@ -485,14 +562,17 @@ imx_uart_bus_transmit(struct uart_softc bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); - /* Fill TX FIFO */ + /* + * Fill the tx fifo. The uart core puts at most IMX_TXFIFO_LEVEL bytes + * into the txbuf (because that's what sc_txfifosz is set to), and + * because we got the TRDY (low-water reached) interrupt we know at + * least that much space is available in the fifo. + */ for (i = 0; i < sc->sc_txdatasz; i++) { SETREG(bas, REG(UTXD), sc->sc_txbuf[i] & 0xff); } - sc->sc_txbusy = 1; - /* Call me when ready */ - ENA(bas, UCR1, TXMPTYEN); + ENA(bas, UCR1, TRDYEN); uart_unlock(sc->sc_hwmtx); @@ -506,7 +586,8 @@ imx_uart_bus_grab(struct uart_softc *sc) bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); - DIS(bas, UCR4, DREN); + DIS(bas, UCR1, RRDYEN); + DIS(bas, UCR2, ATEN); uart_unlock(sc->sc_hwmtx); } @@ -517,6 +598,7 @@ imx_uart_bus_ungrab(struct uart_softc *s bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); - ENA(bas, UCR4, DREN); + ENA(bas, UCR1, RRDYEN); + ENA(bas, UCR2, ATEN); uart_unlock(sc->sc_hwmtx); }
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