Date: Wed, 28 Sep 2011 23:49:22 -0700 From: Juli Mallett <jmallett@FreeBSD.org> To: "Jayachandran C." <c.jayachandran@gmail.com> Cc: freebsd-mips@freebsd.org Subject: Re: eventtimer issue on mips: temporary workaround Message-ID: <CACVs6=8pb_bf0QHhciGjUD30dp1rg3ft77NDtHqeQHJk57CvBg@mail.gmail.com> In-Reply-To: <CA%2B7sy7DpEEhZ7WGoT-p9FCgvGBAeBHnyGVXmcUtHs%2BTt6tsTng@mail.gmail.com> References: <CAJ-Vmo=qONOffCTgusWtbwuo43zKYyXDqqu5YEaL-MDQSbt-mQ@mail.gmail.com> <CAJ-Vmo=i6-3PNTPbP5xCftNU0w1OmMhZSysgaSRzDqgwLU6prQ@mail.gmail.com> <CA%2B7sy7DpEEhZ7WGoT-p9FCgvGBAeBHnyGVXmcUtHs%2BTt6tsTng@mail.gmail.com>
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On Wed, Sep 28, 2011 at 23:41, Jayachandran C. <c.jayachandran@gmail.com> wrote: > the amd implementation seems to be using the STI instruction to enable > interrupts - but I'm not able to see how to avoid this race condition > on platforms which does not have a similar instruction. If I'm understanding right, that's much of the thrust of the problem. I mean, we can check whether a non-masked interrupt was asserted before doing the wait, but there's still a window between that and the wait. It sounds like we need a conditional wait instruction, which is to say it sounds like the code does need a rethink for MIPS (although why "wait" wouldn't return immediately if there's a non-masked interrupt asserted is beyond me.) But I'm still somewhat confused by the original post, so may be missing the mark on that.home | help
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