Date: Sun, 25 Aug 2013 10:15:16 GMT From: zcore@FreeBSD.org To: svn-soc-all@FreeBSD.org Subject: socsvn commit: r256483 - soc2013/zcore/head/usr.sbin/bhyve Message-ID: <201308251015.r7PAFGHH073583@socsvn.freebsd.org>
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Author: zcore Date: Sun Aug 25 10:15:16 2013 New Revision: 256483 URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=256483 Log: use PRIx64 instead of lx Improve portability. bhyve may be run on 32bit system in the future, who knows. Modified: soc2013/zcore/head/usr.sbin/bhyve/pci_ahci.c Modified: soc2013/zcore/head/usr.sbin/bhyve/pci_ahci.c ============================================================================== --- soc2013/zcore/head/usr.sbin/bhyve/pci_ahci.c Sun Aug 25 09:58:31 2013 (r256482) +++ soc2013/zcore/head/usr.sbin/bhyve/pci_ahci.c Sun Aug 25 10:15:16 2013 (r256483) @@ -46,6 +46,7 @@ #include <unistd.h> #include <assert.h> #include <pthread.h> +#include <inttypes.h> #include "bhyverun.h" #include "pci_emul.h" @@ -333,7 +334,7 @@ /* dump prdt, will be removed latter */ for (i = 0; i < hdr->prdtl; i++) { - dprintf("%d@%08lx, %d\n", prdt->dbc & 0x3fffff, prdt->dba, (prdt->dbc >> 31) & 0x1); + dprintf("%d@%08"PRIx64", %d\n", prdt->dbc & 0x3fffff, prdt->dba, (prdt->dbc >> 31) & 0x1); prdt++; } } @@ -433,7 +434,7 @@ offset = (offset - AHCI_OFFSET) % AHCI_STEP; struct ahci_port *p = &sc->port[port]; - DPRINTF(("pci_ahci_port %d: write offset 0x%lx value 0x%lx\n\r", + DPRINTF(("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n\r", port, offset, value)); switch (offset) { case AHCI_P_CLB: @@ -495,7 +496,7 @@ case AHCI_P_TFD: case AHCI_P_SIG: case AHCI_P_SSTS: - WPRINTF(("pci_ahci_port: read only registers 0x%lx\n", offset)); + WPRINTF(("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset)); break; case AHCI_P_SCTL: if (!(p->cmd & AHCI_P_CMD_ST)) { @@ -524,7 +525,7 @@ static void pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value) { - DPRINTF(("pci_ahci_host: write offset 0x%lx value 0x%lx\n\r", + DPRINTF(("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n\r", offset, value)); switch (offset) { @@ -532,7 +533,7 @@ case AHCI_PI: case AHCI_VS: case AHCI_CAP2: - WPRINTF(("pci_ahci_host: read only registers 0x%lx\n", offset)); + WPRINTF(("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset)); break; case AHCI_GHC: if (value & AHCI_GHC_HR) @@ -567,7 +568,7 @@ else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP) pci_ahci_port_write(sc, offset, value); else - DPRINTF(("pci_ahci: unknown i/o write offset 0x%lx\n\r", offset)); + DPRINTF(("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n\r", offset)); pthread_mutex_unlock(&sc->mtx); } @@ -598,7 +599,7 @@ value = 0; break; } - DPRINTF(("pci_ahci_host: read offset 0x%lx value 0x%x\n\r", + DPRINTF(("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n\r", offset, value)); return (value); @@ -640,7 +641,7 @@ value = 0; break; } - DPRINTF(("pci_ahci_port %d: read offset 0x%lx value 0x%x\n\r", + DPRINTF(("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n\r", port, offset, value)); return value; @@ -663,7 +664,7 @@ else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP) value = pci_ahci_port_read(sc, offset); else - DPRINTF(("pci_ahci: unknown i/o read offset 0x%lx\n\r", offset)); + DPRINTF(("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n\r", offset)); pthread_mutex_unlock(&sc->mtx);help
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