Date: Sun, 27 Jan 2019 14:27:54 +0000 (UTC) From: Andriy Voskoboinyk <avos@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-11@freebsd.org Subject: svn commit: r343493 - in stable/11/sys/dev/ath/ath_hal: . ah_regdomain Message-ID: <201901271427.x0RERsUc037616@repo.freebsd.org>
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Author: avos Date: Sun Jan 27 14:27:53 2019 New Revision: 343493 URL: https://svnweb.freebsd.org/changeset/base/343493 Log: MFC r306323: [ath_hal] Add FCC6_FCCA regulatory domain (0x0014). PR: 194336 Requested by: Chris Hutchinson <portmaster@bsdforge.com> Modified: stable/11/sys/dev/ath/ath_hal/ah_internal.h stable/11/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_domains.h stable/11/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_freqbands.h stable/11/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_regmap.h Directory Properties: stable/11/ (props changed) Modified: stable/11/sys/dev/ath/ath_hal/ah_internal.h ============================================================================== --- stable/11/sys/dev/ath/ath_hal/ah_internal.h Sun Jan 27 14:03:38 2019 (r343492) +++ stable/11/sys/dev/ath/ath_hal/ah_internal.h Sun Jan 27 14:27:53 2019 (r343493) @@ -134,7 +134,7 @@ struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, * right now. */ #ifndef AH_MAXCHAN -#define AH_MAXCHAN 96 +#define AH_MAXCHAN 128 #endif #define HAL_NF_CAL_HIST_LEN_FULL 5 Modified: stable/11/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_domains.h ============================================================================== --- stable/11/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_domains.h Sun Jan 27 14:03:38 2019 (r343492) +++ stable/11/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_domains.h Sun Jan 27 14:27:53 2019 (r343493) @@ -242,6 +242,17 @@ static REG_DOMAIN regDomains[] = { .chan11a_quarter = BM3(F8_5180_5240, F8_5260_5320,F10_5745_5825), }, + {.regDmnEnum = FCC6, + .conformanceTestLimit = FCC, + .chan11a = BM5(F8_5180_5240, F5_5260_5320, F1_5500_5580, F2_5660_5720, F6_5745_5825), + .chan11a_turbo = BM3(T7_5210_5210, T3_5250_5290, T2_5760_5800), + .chan11a_dyn_turbo = BM4(T7_5200_5200, T1_5240_5240, T2_5280_5280, T1_5765_5805), +#if 0 + .chan11a_half = BM3(F7_5180_5240, F7_5260_5320, F9_5745_5825), + .chan11a_quarter = BM3(F8_5180_5240, F8_5260_5320,F10_5745_5825), +#endif + }, + {.regDmnEnum = MKK1, .conformanceTestLimit = MKK, .pscan = PSCAN_MKK1, Modified: stable/11/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_freqbands.h ============================================================================== --- stable/11/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_freqbands.h Sun Jan 27 14:03:38 2019 (r343492) +++ stable/11/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_freqbands.h Sun Jan 27 14:27:53 2019 (r343493) @@ -125,8 +125,11 @@ static REG_DMN_FREQ_BAND regDmn5GhzFreq[] = { { 5280, 5320, 17, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, #define F1_5280_5320 AFTER(F3_5260_5700) + { 5500, 5580, 23, 6, 20, 20, DFS_FCC3, PSCAN_FCC }, +#define F1_5500_5580 AFTER(F1_5280_5320) + { 5500, 5620, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI }, -#define F1_5500_5620 AFTER(F1_5280_5320) +#define F1_5500_5620 AFTER(F1_5500_5580) { 5500, 5700, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, #define F1_5500_5700 AFTER(F1_5500_5620) @@ -136,9 +139,11 @@ static REG_DMN_FREQ_BAND regDmn5GhzFreq[] = { #define F3_5500_5700 AFTER(F2_5500_5700) { 5500, 5700, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_MKK3 | PSCAN_FCC }, #define F4_5500_5700 AFTER(F3_5500_5700) + { 5660, 5720, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI }, +#define F2_5660_5720 AFTER(F4_5500_5700) { 5745, 5805, 23, 0, 20, 20, NO_DFS, NO_PSCAN }, -#define F1_5745_5805 AFTER(F4_5500_5700) +#define F1_5745_5805 AFTER(F2_5660_5720) { 5745, 5805, 30, 6, 20, 20, NO_DFS, NO_PSCAN }, #define F2_5745_5805 AFTER(F1_5745_5805) { 5745, 5805, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI }, @@ -191,6 +196,7 @@ static REG_DMN_FREQ_BAND regDmn5GhzFreq[] = { #define W2_5825_5825 AFTER(W2_5180_5240) }; + /* * 5GHz Turbo (dynamic & static) tags */ @@ -203,13 +209,14 @@ static REG_DMN_FREQ_BAND regDmn5GhzTurboFreq[] = { #define T1_5370_5490 AFTER(T1_5250_5330) { 5530, 5650, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN }, #define T1_5530_5650 AFTER(T1_5370_5490) - + { 5200, 5200, 23, 6, 40, 40, NO_DFS, NO_PSCAN }, +#define T7_5200_5200 AFTER(T1_5530_5650) { 5150, 5190, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, -#define T1_5150_5190 AFTER(T1_5530_5650) - { 5230, 5310, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN }, -#define T1_5230_5310 AFTER(T1_5150_5190) +#define T1_5230_5310 AFTER(T7_5200_5200) { 5350, 5470, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, -#define T1_5350_5470 AFTER(T1_5230_5310) +#define T1_5150_5190 AFTER(T1_5230_5310) + { 5230, 5310, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN }, +#define T1_5350_5470 AFTER(T1_5150_5190) { 5510, 5670, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN }, #define T1_5510_5670 AFTER(T1_5350_5470) @@ -221,9 +228,13 @@ static REG_DMN_FREQ_BAND regDmn5GhzTurboFreq[] = { #define T1_5210_5210 AFTER(T2_5200_5240) { 5210, 5210, 23, 0, 40, 40, NO_DFS, NO_PSCAN }, #define T2_5210_5210 AFTER(T1_5210_5210) + { 5210, 5210, 23, 6, 40, 40, NO_DFS, NO_PSCAN }, +#define T7_5210_5210 AFTER(T2_5210_5210) + { 5240, 5240, 23, 6, 40, 40, NO_DFS, PSCAN_FCC_T }, +#define T1_5240_5240 AFTER(T7_5210_5210) { 5280, 5280, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T }, -#define T1_5280_5280 AFTER(T2_5210_5210) +#define T1_5280_5280 AFTER(T1_5240_5240) { 5280, 5280, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T }, #define T2_5280_5280 AFTER(T1_5280_5280) { 5250, 5250, 17, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T }, @@ -234,9 +245,11 @@ static REG_DMN_FREQ_BAND regDmn5GhzTurboFreq[] = { #define T1_5250_5290 AFTER(T1_5290_5290) { 5250, 5290, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T }, #define T2_5250_5290 AFTER(T1_5250_5290) + { 5250, 5290, 23, 6, 40, 40, NO_DFS, PSCAN_FCC_T }, +#define T3_5250_5290 AFTER(T2_5250_5290) { 5540, 5660, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T }, -#define T1_5540_5660 AFTER(T2_5250_5290) +#define T1_5540_5660 AFTER(T3_5250_5290) { 5760, 5800, 20, 0, 40, 40, NO_DFS, NO_PSCAN }, #define T1_5760_5800 AFTER(T1_5540_5660) { 5760, 5800, 30, 6, 40, 40, NO_DFS, NO_PSCAN }, Modified: stable/11/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_regmap.h ============================================================================== --- stable/11/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_regmap.h Sun Jan 27 14:03:38 2019 (r343492) +++ stable/11/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_regmap.h Sun Jan 27 14:27:53 2019 (r343493) @@ -41,6 +41,7 @@ static REG_DMN_PAIR_MAPPING regDomainPairs[] = { {FCC3_WORLD, FCC3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, {FCC4_FCCA, FCC4, FCCA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, {FCC5_FCCB, FCC5, FCCB, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, + {FCC6_FCCA, FCC6, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, {ETSI1_WORLD, ETSI1, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, {ETSI2_WORLD, ETSI2, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT },
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