Date: Tue, 12 Dec 2017 03:16:10 +0000 (UTC) From: Justin Hibbits <jhibbits@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r326789 - head/sys/powerpc/powerpc Message-ID: <201712120316.vBC3GAoh009154@repo.freebsd.org>
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Author: jhibbits Date: Tue Dec 12 03:16:10 2017 New Revision: 326789 URL: https://svnweb.freebsd.org/changeset/base/326789 Log: Decode some PowerPC trap registers Decode on Book-E: * ESR (Exception Syndrome Register) * MCSR (Machine Check Status Register) On AIM: * MSSSR (Memory Subsystem Status Register) Makes it easier to tell at a glance the type of trap and machine check conditions now. Modified: head/sys/powerpc/powerpc/trap.c Modified: head/sys/powerpc/powerpc/trap.c ============================================================================== --- head/sys/powerpc/powerpc/trap.c Tue Dec 12 01:20:45 2017 (r326788) +++ head/sys/powerpc/powerpc/trap.c Tue Dec 12 03:16:10 2017 (r326789) @@ -146,6 +146,26 @@ static struct powerpc_exception powerpc_exceptions[] = { EXC_LAST, NULL } }; +#define ESR_BITMASK \ + "\20" \ + "\040b0\037b1\036b2\035b3\034PIL\033PRR\032PTR\031FP" \ + "\030ST\027b9\026DLK\025ILK\024b12\023b13\022BO\021PIE" \ + "\020b16\017b17\016b18\015b19\014b20\013b21\012b22\011b23" \ + "\010SPE\007EPID\006b26\005b27\004b28\003b29\002b30\001b31" +#define MCSR_BITMASK \ + "\20" \ + "\040MCP\037ICERR\036DCERR\035TLBPERR\034L2MMU_MHIT\033b5\032b6\031b7" \ + "\030b8\027b9\026b10\025NMI\024MAV\023MEA\022b14\021IF" \ + "\020LD\017ST\016LDG\015b19\014b20\013b21\012b22\011b23" \ + "\010b24\007b25\006b26\005b27\004b28\003b29\002TLBSYNC\001BSL2_ERR" +#define MSSSR_BITMASK \ + "\20" \ + "\040b0\037b1\036b2\035b3\034b4\033b5\032b6\031b7" \ + "\030b8\027b9\026b10\025b11\024b12\023L2TAG\022L2DAT\021L3TAG" \ + "\020L3DAT\017APE\016DPE\015TEA\014b20\013b21\012b22\011b23" \ + "\010b24\007b25\006b26\005b27\004b28\003b29\002b30\001b31" + + static const char * trapname(u_int vector) { @@ -443,19 +463,20 @@ printtrap(u_int vector, struct trapframe *frame, int i ver = mfpvr() >> 16; #if defined(AIM) if (MPC745X_P(ver)) - printf(" msssr0 = 0x%lx\n", - (u_long)mfspr(SPR_MSSSR0)); + printf(" msssr0 = 0x%b\n", + (int)mfspr(SPR_MSSSR0), MSSSR_BITMASK); #elif defined(BOOKE) pa = mfspr(SPR_MCARU); pa = (pa << 32) | (u_register_t)mfspr(SPR_MCAR); - printf(" mcsr = 0x%lx\n", (u_long)mfspr(SPR_MCSR)); + printf(" mcsr = 0x%b\n", + (int)mfspr(SPR_MCSR), MCSR_BITMASK); printf(" mcar = 0x%jx\n", (uintmax_t)pa); #endif break; } #ifdef BOOKE - printf(" esr = 0x%" PRIxPTR "\n", - frame->cpu.booke.esr); + printf(" esr = 0x%b\n", + (int)frame->cpu.booke.esr, ESR_BITMASK); #endif printf(" srr0 = 0x%" PRIxPTR "\n", frame->srr0); printf(" srr1 = 0x%lx\n", (u_long)frame->srr1);
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