Date: Wed, 17 Jan 2001 10:28:03 -0800 (PST) From: John Baldwin <jhb@FreeBSD.org> To: Poul-Henning Kamp <phk@critter.freebsd.dk> Cc: Peter Jeremy <peter.jeremy@alcatel.com.au>, current@FreeBSD.org, Garrett Wollman <wollman@khavrinen.lcs.mit.edu>, Robert Drehmel <robert@gizmo.quizbot.org> Subject: Re: Atomic breakage? Message-ID: <XFMail.010117102803.jhb@FreeBSD.org> In-Reply-To: <53512.979753444@critter>
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On 17-Jan-01 Poul-Henning Kamp wrote: > In message <3A65D810.6304785A@gizmo.quizbot.org>, Robert Drehmel writes: >>In <XFMail.010117084010.jhb@FreeBSD.org>, John Baldwin wrote: >>> Early Pentiums (<= P90) don't support CX8 or so I've heard, which make this >>> slightly more complicated, as for a pentium we would have to use a function >>> pointer that we setup during probe. Also, during a SMP boot we would have >>> to >>> panic if CX8 wasn't enabled on all CPU's. >> >>P75 (stepping 5): <FPU,VME,DE,PSE,TSC,MSR,MCE,CX8> >> >>cmpxchg8 was actually introduced with the Pentium processors, >>as Mr. Wollman already wrote. > > Either way, it's precense should be determined by looking at the CPUID > feature bit. It's the only reliable way. It's expensive though. Ok, after some digging I found out what this particular person was referring to: on Pentiums with stepping < 0xc, a cmpxchg8b that crosses a page boundary triggers an illegel opcode fault rather than a page fault if the second page is missing. Woo. :) So as long as we keep all atomically-accessed 64-bit integers within a single page we should be fine for CX8 on all pentiums should we even want 64-bit atomic ops. -- John Baldwin <jhb@FreeBSD.org> -- http://www.FreeBSD.org/~jhb/ PGP Key: http://www.baldwin.cx/~john/pgpkey.asc "Power Users Use the Power to Serve!" - http://www.FreeBSD.org/ To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-current" in the body of the message
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