Skip site navigation (1)Skip section navigation (2)
Date:      Fri, 16 Jun 2017 21:04:14 +0000 (UTC)
From:      Dimitry Andric <dim@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org
Subject:   svn commit: r320021 - in vendor/lld/dist: COFF ELF ELF/Arch docs test test/COFF test/COFF/Inputs test/ELF test/ELF/Inputs test/ELF/linkerscript
Message-ID:  <201706162104.v5GL4E3H063811@repo.freebsd.org>

next in thread | raw e-mail | index | archive | help
Author: dim
Date: Fri Jun 16 21:04:14 2017
New Revision: 320021
URL: https://svnweb.freebsd.org/changeset/base/320021

Log:
  Vendor import of lld trunk r305575:
  https://llvm.org/svn/llvm-project/lld/trunk@305575

Added:
  vendor/lld/dist/ELF/Arch/
  vendor/lld/dist/ELF/Arch/AArch64.cpp   (contents, props changed)
  vendor/lld/dist/ELF/Arch/AMDGPU.cpp   (contents, props changed)
  vendor/lld/dist/ELF/Arch/ARM.cpp   (contents, props changed)
  vendor/lld/dist/ELF/Arch/AVR.cpp   (contents, props changed)
  vendor/lld/dist/ELF/Arch/Mips.cpp   (contents, props changed)
  vendor/lld/dist/ELF/Arch/PPC.cpp   (contents, props changed)
  vendor/lld/dist/ELF/Arch/PPC64.cpp   (contents, props changed)
  vendor/lld/dist/ELF/Arch/X86.cpp   (contents, props changed)
  vendor/lld/dist/ELF/Arch/X86_64.cpp   (contents, props changed)
  vendor/lld/dist/test/COFF/Inputs/library.def
  vendor/lld/dist/test/COFF/lib.test
  vendor/lld/dist/test/COFF/pdb-lib.s   (contents, props changed)
  vendor/lld/dist/test/ELF/Inputs/icf-merge-sec.s   (contents, props changed)
  vendor/lld/dist/test/ELF/Inputs/icf-merge.s   (contents, props changed)
  vendor/lld/dist/test/ELF/Inputs/icf-merge2.s   (contents, props changed)
  vendor/lld/dist/test/ELF/Inputs/icf-merge3.s   (contents, props changed)
  vendor/lld/dist/test/ELF/Inputs/sht-group-gold-r.elf   (contents, props changed)
  vendor/lld/dist/test/ELF/Inputs/sht-group-gold-r.s   (contents, props changed)
  vendor/lld/dist/test/ELF/basic-avr.s   (contents, props changed)
  vendor/lld/dist/test/ELF/icf-merge-sec.s   (contents, props changed)
  vendor/lld/dist/test/ELF/icf-merge.s   (contents, props changed)
  vendor/lld/dist/test/ELF/linkerscript/data-commands-gc.s   (contents, props changed)
  vendor/lld/dist/test/ELF/sht-group-gold-r.test
Modified:
  vendor/lld/dist/COFF/Driver.cpp
  vendor/lld/dist/COFF/DriverUtils.cpp
  vendor/lld/dist/COFF/InputFiles.h
  vendor/lld/dist/COFF/PDB.cpp
  vendor/lld/dist/ELF/CMakeLists.txt
  vendor/lld/dist/ELF/Driver.cpp
  vendor/lld/dist/ELF/ICF.cpp
  vendor/lld/dist/ELF/InputFiles.cpp
  vendor/lld/dist/ELF/InputFiles.h
  vendor/lld/dist/ELF/InputSection.cpp
  vendor/lld/dist/ELF/LinkerScript.cpp
  vendor/lld/dist/ELF/LinkerScript.h
  vendor/lld/dist/ELF/MarkLive.cpp
  vendor/lld/dist/ELF/OutputSections.cpp
  vendor/lld/dist/ELF/OutputSections.h
  vendor/lld/dist/ELF/Relocations.cpp
  vendor/lld/dist/ELF/Relocations.h
  vendor/lld/dist/ELF/Strings.h
  vendor/lld/dist/ELF/SyntheticSections.cpp
  vendor/lld/dist/ELF/SyntheticSections.h
  vendor/lld/dist/ELF/Target.cpp
  vendor/lld/dist/ELF/Target.h
  vendor/lld/dist/ELF/Writer.cpp
  vendor/lld/dist/docs/windows_support.rst
  vendor/lld/dist/test/COFF/Inputs/constant-export.ll
  vendor/lld/dist/test/COFF/Inputs/pdb1.yaml
  vendor/lld/dist/test/COFF/Inputs/pdb2.yaml
  vendor/lld/dist/test/COFF/include-lto.ll
  vendor/lld/dist/test/COFF/lto-linker-opts.ll
  vendor/lld/dist/test/COFF/pdb-none.test
  vendor/lld/dist/test/COFF/pdb-options.test
  vendor/lld/dist/test/COFF/pdb.test
  vendor/lld/dist/test/COFF/sort-debug.test
  vendor/lld/dist/test/ELF/aarch64-undefined-weak.s
  vendor/lld/dist/test/ELF/arm-thumb-no-undefined-thunk.s
  vendor/lld/dist/test/ELF/arm-thumb-undefined-weak.s
  vendor/lld/dist/test/ELF/arm-undefined-weak.s
  vendor/lld/dist/test/ELF/linkerscript/locationcountererr2.s
  vendor/lld/dist/test/ELF/linkerscript/symbols-non-alloc.s
  vendor/lld/dist/test/lit.cfg

Modified: vendor/lld/dist/COFF/Driver.cpp
==============================================================================
--- vendor/lld/dist/COFF/Driver.cpp	Fri Jun 16 21:04:10 2017	(r320020)
+++ vendor/lld/dist/COFF/Driver.cpp	Fri Jun 16 21:04:14 2017	(r320021)
@@ -429,7 +429,7 @@ static std::string getImplibPath() {
   return Out.str();
 }
 
-std::vector<COFFShortExport> createCOFFShortExportFromConfig() {
+static void createImportLibrary() {
   std::vector<COFFShortExport> Exports;
   for (Export &E1 : Config->Exports) {
     COFFShortExport E2;
@@ -443,11 +443,7 @@ std::vector<COFFShortExport> createCOFFShortExportFrom
     E2.Constant = E1.Constant;
     Exports.push_back(E2);
   }
-  return Exports;
-}
 
-static void createImportLibrary() {
-  std::vector<COFFShortExport> Exports = createCOFFShortExportFromConfig();
   std::string DLLName = sys::path::filename(Config->OutputFile);
   std::string Path = getImplibPath();
   writeImportLibrary(DLLName, Path, Exports, Config->Machine);
@@ -707,8 +703,12 @@ void LinkerDriver::link(ArrayRef<const char *> ArgsArr
     }
   }
 
-  if (!Args.hasArgNoClaim(OPT_INPUT))
-    fatal("no input files");
+  if (!Args.hasArgNoClaim(OPT_INPUT)) {
+    if (Args.hasArgNoClaim(OPT_deffile))
+      Config->NoEntry = true;
+    else
+      fatal("no input files");
+  }
 
   // Construct search path list.
   SearchPaths.push_back("");
@@ -988,6 +988,13 @@ void LinkerDriver::link(ArrayRef<const char *> ArgsArr
   if (auto *Arg = Args.getLastArg(OPT_deffile)) {
     // parseModuleDefs mutates Config object.
     parseModuleDefs(Arg->getValue());
+  }
+
+  // Handle generation of import library from a def file.
+  if (!Args.hasArgNoClaim(OPT_INPUT)) {
+    fixupExports();
+    createImportLibrary();
+    exit(0);
   }
 
   // Handle /delayload

Modified: vendor/lld/dist/COFF/DriverUtils.cpp
==============================================================================
--- vendor/lld/dist/COFF/DriverUtils.cpp	Fri Jun 16 21:04:10 2017	(r320020)
+++ vendor/lld/dist/COFF/DriverUtils.cpp	Fri Jun 16 21:04:14 2017	(r320021)
@@ -522,7 +522,7 @@ void fixupExports() {
 
   for (Export &E : Config->Exports) {
     SymbolBody *Sym = E.Sym;
-    if (!E.ForwardTo.empty()) {
+    if (!E.ForwardTo.empty() || !Sym) {
       E.SymbolName = E.Name;
     } else {
       if (auto *U = dyn_cast<Undefined>(Sym))

Modified: vendor/lld/dist/COFF/InputFiles.h
==============================================================================
--- vendor/lld/dist/COFF/InputFiles.h	Fri Jun 16 21:04:10 2017	(r320020)
+++ vendor/lld/dist/COFF/InputFiles.h	Fri Jun 16 21:04:14 2017	(r320021)
@@ -22,6 +22,12 @@
 #include <set>
 #include <vector>
 
+namespace llvm {
+namespace pdb {
+class DbiModuleDescriptorBuilder;
+}
+}
+
 namespace lld {
 namespace coff {
 
@@ -121,6 +127,12 @@ class ObjectFile : public InputFile { (public)
   // The list of safe exception handlers listed in .sxdata section.
   // COFF-specific and x86-only.
   std::set<SymbolBody *> SEHandlers;
+
+  // Pointer to the PDB module descriptor builder. Various debug info records
+  // will reference object files by "module index", which is here. Things like
+  // source files and section contributions are also recorded here. Will be null
+  // if we are not producing a PDB.
+  llvm::pdb::DbiModuleDescriptorBuilder *ModuleDBI = nullptr;
 
 private:
   void initializeChunks();

Modified: vendor/lld/dist/COFF/PDB.cpp
==============================================================================
--- vendor/lld/dist/COFF/PDB.cpp	Fri Jun 16 21:04:10 2017	(r320020)
+++ vendor/lld/dist/COFF/PDB.cpp	Fri Jun 16 21:04:14 2017	(r320021)
@@ -29,6 +29,7 @@
 #include "llvm/DebugInfo/PDB/Native/InfoStreamBuilder.h"
 #include "llvm/DebugInfo/PDB/Native/PDBFile.h"
 #include "llvm/DebugInfo/PDB/Native/PDBFileBuilder.h"
+#include "llvm/DebugInfo/PDB/Native/DbiModuleDescriptorBuilder.h"
 #include "llvm/DebugInfo/PDB/Native/PDBStringTableBuilder.h"
 #include "llvm/DebugInfo/PDB/Native/PDBTypeServerHandler.h"
 #include "llvm/DebugInfo/PDB/Native/TpiStream.h"
@@ -53,12 +54,10 @@ using llvm::object::coff_section;
 static ExitOnError ExitOnErr;
 
 // Returns a list of all SectionChunks.
-static std::vector<coff_section> getInputSections(SymbolTable *Symtab) {
-  std::vector<coff_section> V;
+static void addSectionContribs(SymbolTable *Symtab, pdb::DbiStreamBuilder &DbiBuilder) {
   for (Chunk *C : Symtab->getChunks())
     if (auto *SC = dyn_cast<SectionChunk>(C))
-      V.push_back(*SC->Header);
-  return V;
+      DbiBuilder.addSectionContrib(SC->File->ModuleDBI, SC->Header);
 }
 
 static SectionChunk *findByName(std::vector<SectionChunk *> &Sections,
@@ -95,10 +94,11 @@ static void addTypeInfo(pdb::TpiStreamBuilder &TpiBuil
   });
 }
 
-// Merge .debug$T sections into IpiData and TpiData.
-static void mergeDebugT(SymbolTable *Symtab, pdb::PDBFileBuilder &Builder,
-                        codeview::TypeTableBuilder &TypeTable,
-                        codeview::TypeTableBuilder &IDTable) {
+// Add all object files to the PDB. Merge .debug$T sections into IpiData and
+// TpiData.
+static void addObjectsToPDB(SymbolTable *Symtab, pdb::PDBFileBuilder &Builder,
+                            codeview::TypeTableBuilder &TypeTable,
+                            codeview::TypeTableBuilder &IDTable) {
   // Follow type servers.  If the same type server is encountered more than
   // once for this instance of `PDBTypeServerHandler` (for example if many
   // object files reference the same TypeServer), the types from the
@@ -107,6 +107,20 @@ static void mergeDebugT(SymbolTable *Symtab, pdb::PDBF
 
   // Visit all .debug$T sections to add them to Builder.
   for (ObjectFile *File : Symtab->ObjectFiles) {
+    // Add a module descriptor for every object file. We need to put an absolute
+    // path to the object into the PDB. If this is a plain object, we make its
+    // path absolute. If it's an object in an archive, we make the archive path
+    // absolute.
+    bool InArchive = !File->ParentName.empty();
+    SmallString<128> Path = InArchive ? File->ParentName : File->getName();
+    sys::fs::make_absolute(Path);
+    StringRef Name = InArchive ? File->getName() : StringRef(Path);
+    File->ModuleDBI = &ExitOnErr(Builder.getDbiBuilder().addModuleInfo(Name));
+    File->ModuleDBI->setObjFileName(Path);
+
+    // FIXME: Walk the .debug$S sections and add them. Do things like recording
+    // source files.
+
     ArrayRef<uint8_t> Data = getDebugSection(File, ".debug$T");
     if (Data.empty())
       continue;
@@ -202,17 +216,15 @@ void coff::createPDB(StringRef Path, SymbolTable *Symt
   InfoBuilder.setVersion(pdb::PdbRaw_ImplVer::PdbImplVC70);
 
   // Add an empty DPI stream.
-  auto &DbiBuilder = Builder.getDbiBuilder();
+  pdb::DbiStreamBuilder &DbiBuilder = Builder.getDbiBuilder();
   DbiBuilder.setVersionHeader(pdb::PdbDbiV110);
 
   codeview::TypeTableBuilder TypeTable(BAlloc);
   codeview::TypeTableBuilder IDTable(BAlloc);
-  mergeDebugT(Symtab, Builder, TypeTable, IDTable);
+  addObjectsToPDB(Symtab, Builder, TypeTable, IDTable);
 
   // Add Section Contributions.
-  std::vector<pdb::SectionContrib> Contribs =
-      pdb::DbiStreamBuilder::createSectionContribs(getInputSections(Symtab));
-  DbiBuilder.setSectionContribs(Contribs);
+  addSectionContribs(Symtab, DbiBuilder);
 
   // Add Section Map stream.
   ArrayRef<object::coff_section> Sections = {

Added: vendor/lld/dist/ELF/Arch/AArch64.cpp
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ vendor/lld/dist/ELF/Arch/AArch64.cpp	Fri Jun 16 21:04:14 2017	(r320021)
@@ -0,0 +1,374 @@
+//===- AArch64.cpp --------------------------------------------------------===//
+//
+//                             The LLVM Linker
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "Error.h"
+#include "Memory.h"
+#include "Symbols.h"
+#include "SyntheticSections.h"
+#include "Target.h"
+#include "Thunks.h"
+#include "llvm/Object/ELF.h"
+#include "llvm/Support/Endian.h"
+
+using namespace llvm;
+using namespace llvm::support::endian;
+using namespace llvm::ELF;
+using namespace lld;
+using namespace lld::elf;
+
+// Page(Expr) is the page address of the expression Expr, defined
+// as (Expr & ~0xFFF). (This applies even if the machine page size
+// supported by the platform has a different value.)
+uint64_t elf::getAArch64Page(uint64_t Expr) {
+  return Expr & ~static_cast<uint64_t>(0xFFF);
+}
+
+namespace {
+class AArch64 final : public TargetInfo {
+public:
+  AArch64();
+  RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
+                     const uint8_t *Loc) const override;
+  bool isPicRel(uint32_t Type) const override;
+  void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
+  void writePltHeader(uint8_t *Buf) const override;
+  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
+                int32_t Index, unsigned RelOff) const override;
+  bool usesOnlyLowPageBits(uint32_t Type) const override;
+  void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+  RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
+                          RelExpr Expr) const override;
+  void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+  void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+  void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+};
+} // namespace
+
+AArch64::AArch64() {
+  CopyRel = R_AARCH64_COPY;
+  RelativeRel = R_AARCH64_RELATIVE;
+  IRelativeRel = R_AARCH64_IRELATIVE;
+  GotRel = R_AARCH64_GLOB_DAT;
+  PltRel = R_AARCH64_JUMP_SLOT;
+  TlsDescRel = R_AARCH64_TLSDESC;
+  TlsGotRel = R_AARCH64_TLS_TPREL64;
+  GotEntrySize = 8;
+  GotPltEntrySize = 8;
+  PltEntrySize = 16;
+  PltHeaderSize = 32;
+  DefaultMaxPageSize = 65536;
+
+  // It doesn't seem to be documented anywhere, but tls on aarch64 uses variant
+  // 1 of the tls structures and the tcb size is 16.
+  TcbSize = 16;
+}
+
+RelExpr AArch64::getRelExpr(uint32_t Type, const SymbolBody &S,
+                            const uint8_t *Loc) const {
+  switch (Type) {
+  default:
+    return R_ABS;
+  case R_AARCH64_TLSDESC_ADR_PAGE21:
+    return R_TLSDESC_PAGE;
+  case R_AARCH64_TLSDESC_LD64_LO12:
+  case R_AARCH64_TLSDESC_ADD_LO12:
+    return R_TLSDESC;
+  case R_AARCH64_TLSDESC_CALL:
+    return R_TLSDESC_CALL;
+  case R_AARCH64_TLSLE_ADD_TPREL_HI12:
+  case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
+    return R_TLS;
+  case R_AARCH64_CALL26:
+  case R_AARCH64_CONDBR19:
+  case R_AARCH64_JUMP26:
+  case R_AARCH64_TSTBR14:
+    return R_PLT_PC;
+  case R_AARCH64_PREL16:
+  case R_AARCH64_PREL32:
+  case R_AARCH64_PREL64:
+  case R_AARCH64_ADR_PREL_LO21:
+    return R_PC;
+  case R_AARCH64_ADR_PREL_PG_HI21:
+    return R_PAGE_PC;
+  case R_AARCH64_LD64_GOT_LO12_NC:
+  case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
+    return R_GOT;
+  case R_AARCH64_ADR_GOT_PAGE:
+  case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
+    return R_GOT_PAGE_PC;
+  case R_AARCH64_NONE:
+    return R_NONE;
+  }
+}
+
+RelExpr AArch64::adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
+                                 RelExpr Expr) const {
+  if (Expr == R_RELAX_TLS_GD_TO_IE) {
+    if (Type == R_AARCH64_TLSDESC_ADR_PAGE21)
+      return R_RELAX_TLS_GD_TO_IE_PAGE_PC;
+    return R_RELAX_TLS_GD_TO_IE_ABS;
+  }
+  return Expr;
+}
+
+bool AArch64::usesOnlyLowPageBits(uint32_t Type) const {
+  switch (Type) {
+  default:
+    return false;
+  case R_AARCH64_ADD_ABS_LO12_NC:
+  case R_AARCH64_LD64_GOT_LO12_NC:
+  case R_AARCH64_LDST128_ABS_LO12_NC:
+  case R_AARCH64_LDST16_ABS_LO12_NC:
+  case R_AARCH64_LDST32_ABS_LO12_NC:
+  case R_AARCH64_LDST64_ABS_LO12_NC:
+  case R_AARCH64_LDST8_ABS_LO12_NC:
+  case R_AARCH64_TLSDESC_ADD_LO12:
+  case R_AARCH64_TLSDESC_LD64_LO12:
+  case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
+    return true;
+  }
+}
+
+bool AArch64::isPicRel(uint32_t Type) const {
+  return Type == R_AARCH64_ABS32 || Type == R_AARCH64_ABS64;
+}
+
+void AArch64::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
+  write64le(Buf, InX::Plt->getVA());
+}
+
+void AArch64::writePltHeader(uint8_t *Buf) const {
+  const uint8_t PltData[] = {
+      0xf0, 0x7b, 0xbf, 0xa9, // stp    x16, x30, [sp,#-16]!
+      0x10, 0x00, 0x00, 0x90, // adrp   x16, Page(&(.plt.got[2]))
+      0x11, 0x02, 0x40, 0xf9, // ldr    x17, [x16, Offset(&(.plt.got[2]))]
+      0x10, 0x02, 0x00, 0x91, // add    x16, x16, Offset(&(.plt.got[2]))
+      0x20, 0x02, 0x1f, 0xd6, // br     x17
+      0x1f, 0x20, 0x03, 0xd5, // nop
+      0x1f, 0x20, 0x03, 0xd5, // nop
+      0x1f, 0x20, 0x03, 0xd5  // nop
+  };
+  memcpy(Buf, PltData, sizeof(PltData));
+
+  uint64_t Got = InX::GotPlt->getVA();
+  uint64_t Plt = InX::Plt->getVA();
+  relocateOne(Buf + 4, R_AARCH64_ADR_PREL_PG_HI21,
+              getAArch64Page(Got + 16) - getAArch64Page(Plt + 4));
+  relocateOne(Buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, Got + 16);
+  relocateOne(Buf + 12, R_AARCH64_ADD_ABS_LO12_NC, Got + 16);
+}
+
+void AArch64::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
+                       uint64_t PltEntryAddr, int32_t Index,
+                       unsigned RelOff) const {
+  const uint8_t Inst[] = {
+      0x10, 0x00, 0x00, 0x90, // adrp x16, Page(&(.plt.got[n]))
+      0x11, 0x02, 0x40, 0xf9, // ldr  x17, [x16, Offset(&(.plt.got[n]))]
+      0x10, 0x02, 0x00, 0x91, // add  x16, x16, Offset(&(.plt.got[n]))
+      0x20, 0x02, 0x1f, 0xd6  // br   x17
+  };
+  memcpy(Buf, Inst, sizeof(Inst));
+
+  relocateOne(Buf, R_AARCH64_ADR_PREL_PG_HI21,
+              getAArch64Page(GotPltEntryAddr) - getAArch64Page(PltEntryAddr));
+  relocateOne(Buf + 4, R_AARCH64_LDST64_ABS_LO12_NC, GotPltEntryAddr);
+  relocateOne(Buf + 8, R_AARCH64_ADD_ABS_LO12_NC, GotPltEntryAddr);
+}
+
+static void write32AArch64Addr(uint8_t *L, uint64_t Imm) {
+  uint32_t ImmLo = (Imm & 0x3) << 29;
+  uint32_t ImmHi = (Imm & 0x1FFFFC) << 3;
+  uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3);
+  write32le(L, (read32le(L) & ~Mask) | ImmLo | ImmHi);
+}
+
+// Return the bits [Start, End] from Val shifted Start bits.
+// For instance, getBits(0xF0, 4, 8) returns 0xF.
+static uint64_t getBits(uint64_t Val, int Start, int End) {
+  uint64_t Mask = ((uint64_t)1 << (End + 1 - Start)) - 1;
+  return (Val >> Start) & Mask;
+}
+
+static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); }
+
+// Update the immediate field in a AARCH64 ldr, str, and add instruction.
+static void or32AArch64Imm(uint8_t *L, uint64_t Imm) {
+  or32le(L, (Imm & 0xFFF) << 10);
+}
+
+void AArch64::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
+  switch (Type) {
+  case R_AARCH64_ABS16:
+  case R_AARCH64_PREL16:
+    checkIntUInt<16>(Loc, Val, Type);
+    write16le(Loc, Val);
+    break;
+  case R_AARCH64_ABS32:
+  case R_AARCH64_PREL32:
+    checkIntUInt<32>(Loc, Val, Type);
+    write32le(Loc, Val);
+    break;
+  case R_AARCH64_ABS64:
+  case R_AARCH64_GLOB_DAT:
+  case R_AARCH64_PREL64:
+    write64le(Loc, Val);
+    break;
+  case R_AARCH64_ADD_ABS_LO12_NC:
+    or32AArch64Imm(Loc, Val);
+    break;
+  case R_AARCH64_ADR_GOT_PAGE:
+  case R_AARCH64_ADR_PREL_PG_HI21:
+  case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
+  case R_AARCH64_TLSDESC_ADR_PAGE21:
+    checkInt<33>(Loc, Val, Type);
+    write32AArch64Addr(Loc, Val >> 12);
+    break;
+  case R_AARCH64_ADR_PREL_LO21:
+    checkInt<21>(Loc, Val, Type);
+    write32AArch64Addr(Loc, Val);
+    break;
+  case R_AARCH64_CALL26:
+  case R_AARCH64_JUMP26:
+    checkInt<28>(Loc, Val, Type);
+    or32le(Loc, (Val & 0x0FFFFFFC) >> 2);
+    break;
+  case R_AARCH64_CONDBR19:
+    checkInt<21>(Loc, Val, Type);
+    or32le(Loc, (Val & 0x1FFFFC) << 3);
+    break;
+  case R_AARCH64_LD64_GOT_LO12_NC:
+  case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
+  case R_AARCH64_TLSDESC_LD64_LO12:
+    checkAlignment<8>(Loc, Val, Type);
+    or32le(Loc, (Val & 0xFF8) << 7);
+    break;
+  case R_AARCH64_LDST8_ABS_LO12_NC:
+    or32AArch64Imm(Loc, getBits(Val, 0, 11));
+    break;
+  case R_AARCH64_LDST16_ABS_LO12_NC:
+    or32AArch64Imm(Loc, getBits(Val, 1, 11));
+    break;
+  case R_AARCH64_LDST32_ABS_LO12_NC:
+    or32AArch64Imm(Loc, getBits(Val, 2, 11));
+    break;
+  case R_AARCH64_LDST64_ABS_LO12_NC:
+    or32AArch64Imm(Loc, getBits(Val, 3, 11));
+    break;
+  case R_AARCH64_LDST128_ABS_LO12_NC:
+    or32AArch64Imm(Loc, getBits(Val, 4, 11));
+    break;
+  case R_AARCH64_MOVW_UABS_G0_NC:
+    or32le(Loc, (Val & 0xFFFF) << 5);
+    break;
+  case R_AARCH64_MOVW_UABS_G1_NC:
+    or32le(Loc, (Val & 0xFFFF0000) >> 11);
+    break;
+  case R_AARCH64_MOVW_UABS_G2_NC:
+    or32le(Loc, (Val & 0xFFFF00000000) >> 27);
+    break;
+  case R_AARCH64_MOVW_UABS_G3:
+    or32le(Loc, (Val & 0xFFFF000000000000) >> 43);
+    break;
+  case R_AARCH64_TSTBR14:
+    checkInt<16>(Loc, Val, Type);
+    or32le(Loc, (Val & 0xFFFC) << 3);
+    break;
+  case R_AARCH64_TLSLE_ADD_TPREL_HI12:
+    checkInt<24>(Loc, Val, Type);
+    or32AArch64Imm(Loc, Val >> 12);
+    break;
+  case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
+  case R_AARCH64_TLSDESC_ADD_LO12:
+    or32AArch64Imm(Loc, Val);
+    break;
+  default:
+    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
+  }
+}
+
+void AArch64::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
+  // TLSDESC Global-Dynamic relocation are in the form:
+  //   adrp    x0, :tlsdesc:v             [R_AARCH64_TLSDESC_ADR_PAGE21]
+  //   ldr     x1, [x0, #:tlsdesc_lo12:v  [R_AARCH64_TLSDESC_LD64_LO12]
+  //   add     x0, x0, :tlsdesc_los:v     [R_AARCH64_TLSDESC_ADD_LO12]
+  //   .tlsdesccall                       [R_AARCH64_TLSDESC_CALL]
+  //   blr     x1
+  // And it can optimized to:
+  //   movz    x0, #0x0, lsl #16
+  //   movk    x0, #0x10
+  //   nop
+  //   nop
+  checkUInt<32>(Loc, Val, Type);
+
+  switch (Type) {
+  case R_AARCH64_TLSDESC_ADD_LO12:
+  case R_AARCH64_TLSDESC_CALL:
+    write32le(Loc, 0xd503201f); // nop
+    return;
+  case R_AARCH64_TLSDESC_ADR_PAGE21:
+    write32le(Loc, 0xd2a00000 | (((Val >> 16) & 0xffff) << 5)); // movz
+    return;
+  case R_AARCH64_TLSDESC_LD64_LO12:
+    write32le(Loc, 0xf2800000 | ((Val & 0xffff) << 5)); // movk
+    return;
+  default:
+    llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
+  }
+}
+
+void AArch64::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
+  // TLSDESC Global-Dynamic relocation are in the form:
+  //   adrp    x0, :tlsdesc:v             [R_AARCH64_TLSDESC_ADR_PAGE21]
+  //   ldr     x1, [x0, #:tlsdesc_lo12:v  [R_AARCH64_TLSDESC_LD64_LO12]
+  //   add     x0, x0, :tlsdesc_los:v     [R_AARCH64_TLSDESC_ADD_LO12]
+  //   .tlsdesccall                       [R_AARCH64_TLSDESC_CALL]
+  //   blr     x1
+  // And it can optimized to:
+  //   adrp    x0, :gottprel:v
+  //   ldr     x0, [x0, :gottprel_lo12:v]
+  //   nop
+  //   nop
+
+  switch (Type) {
+  case R_AARCH64_TLSDESC_ADD_LO12:
+  case R_AARCH64_TLSDESC_CALL:
+    write32le(Loc, 0xd503201f); // nop
+    break;
+  case R_AARCH64_TLSDESC_ADR_PAGE21:
+    write32le(Loc, 0x90000000); // adrp
+    relocateOne(Loc, R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, Val);
+    break;
+  case R_AARCH64_TLSDESC_LD64_LO12:
+    write32le(Loc, 0xf9400000); // ldr
+    relocateOne(Loc, R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, Val);
+    break;
+  default:
+    llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
+  }
+}
+
+void AArch64::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
+  checkUInt<32>(Loc, Val, Type);
+
+  if (Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) {
+    // Generate MOVZ.
+    uint32_t RegNo = read32le(Loc) & 0x1f;
+    write32le(Loc, (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5));
+    return;
+  }
+  if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) {
+    // Generate MOVK.
+    uint32_t RegNo = read32le(Loc) & 0x1f;
+    write32le(Loc, (0xf2800000 | RegNo) | ((Val & 0xffff) << 5));
+    return;
+  }
+  llvm_unreachable("invalid relocation for TLS IE to LE relaxation");
+}
+
+TargetInfo *elf::createAArch64TargetInfo() { return make<AArch64>(); }

Added: vendor/lld/dist/ELF/Arch/AMDGPU.cpp
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ vendor/lld/dist/ELF/Arch/AMDGPU.cpp	Fri Jun 16 21:04:14 2017	(r320021)
@@ -0,0 +1,82 @@
+//===- AMDGPU.cpp ---------------------------------------------------------===//
+//
+//                             The LLVM Linker
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "Error.h"
+#include "InputFiles.h"
+#include "Memory.h"
+#include "Symbols.h"
+#include "Target.h"
+#include "llvm/Object/ELF.h"
+#include "llvm/Support/Endian.h"
+
+using namespace llvm;
+using namespace llvm::object;
+using namespace llvm::support::endian;
+using namespace llvm::ELF;
+using namespace lld;
+using namespace lld::elf;
+
+namespace {
+class AMDGPU final : public TargetInfo {
+public:
+  AMDGPU();
+  void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+  RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
+                     const uint8_t *Loc) const override;
+};
+} // namespace
+
+AMDGPU::AMDGPU() {
+  RelativeRel = R_AMDGPU_REL64;
+  GotRel = R_AMDGPU_ABS64;
+  GotEntrySize = 8;
+}
+
+void AMDGPU::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
+  switch (Type) {
+  case R_AMDGPU_ABS32:
+  case R_AMDGPU_GOTPCREL:
+  case R_AMDGPU_GOTPCREL32_LO:
+  case R_AMDGPU_REL32:
+  case R_AMDGPU_REL32_LO:
+    write32le(Loc, Val);
+    break;
+  case R_AMDGPU_ABS64:
+    write64le(Loc, Val);
+    break;
+  case R_AMDGPU_GOTPCREL32_HI:
+  case R_AMDGPU_REL32_HI:
+    write32le(Loc, Val >> 32);
+    break;
+  default:
+    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
+  }
+}
+
+RelExpr AMDGPU::getRelExpr(uint32_t Type, const SymbolBody &S,
+                           const uint8_t *Loc) const {
+  switch (Type) {
+  case R_AMDGPU_ABS32:
+  case R_AMDGPU_ABS64:
+    return R_ABS;
+  case R_AMDGPU_REL32:
+  case R_AMDGPU_REL32_LO:
+  case R_AMDGPU_REL32_HI:
+    return R_PC;
+  case R_AMDGPU_GOTPCREL:
+  case R_AMDGPU_GOTPCREL32_LO:
+  case R_AMDGPU_GOTPCREL32_HI:
+    return R_GOT_PC;
+  default:
+    error(toString(S.File) + ": unknown relocation type: " + toString(Type));
+    return R_HINT;
+  }
+}
+
+TargetInfo *elf::createAMDGPUTargetInfo() { return make<AMDGPU>(); }

Added: vendor/lld/dist/ELF/Arch/ARM.cpp
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ vendor/lld/dist/ELF/Arch/ARM.cpp	Fri Jun 16 21:04:14 2017	(r320021)
@@ -0,0 +1,432 @@
+//===- ARM.cpp ------------------------------------------------------------===//
+//
+//                             The LLVM Linker
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "Error.h"
+#include "InputFiles.h"
+#include "Memory.h"
+#include "Symbols.h"
+#include "SyntheticSections.h"
+#include "Target.h"
+#include "Thunks.h"
+#include "llvm/Object/ELF.h"
+#include "llvm/Support/Endian.h"
+
+using namespace llvm;
+using namespace llvm::support::endian;
+using namespace llvm::ELF;
+using namespace lld;
+using namespace lld::elf;
+
+namespace {
+class ARM final : public TargetInfo {
+public:
+  ARM();
+  RelExpr getRelExpr(uint32_t Type, const SymbolBody &S,
+                     const uint8_t *Loc) const override;
+  bool isPicRel(uint32_t Type) const override;
+  uint32_t getDynRel(uint32_t Type) const override;
+  int64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
+  void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
+  void writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const override;
+  void writePltHeader(uint8_t *Buf) const override;
+  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
+                int32_t Index, unsigned RelOff) const override;
+  void addPltSymbols(InputSectionBase *IS, uint64_t Off) const override;
+  void addPltHeaderSymbols(InputSectionBase *ISD) const override;
+  bool needsThunk(RelExpr Expr, uint32_t RelocType, const InputFile *File,
+                  const SymbolBody &S) const override;
+  void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
+};
+} // namespace
+
+ARM::ARM() {
+  CopyRel = R_ARM_COPY;
+  RelativeRel = R_ARM_RELATIVE;
+  IRelativeRel = R_ARM_IRELATIVE;
+  GotRel = R_ARM_GLOB_DAT;
+  PltRel = R_ARM_JUMP_SLOT;
+  TlsGotRel = R_ARM_TLS_TPOFF32;
+  TlsModuleIndexRel = R_ARM_TLS_DTPMOD32;
+  TlsOffsetRel = R_ARM_TLS_DTPOFF32;
+  GotEntrySize = 4;
+  GotPltEntrySize = 4;
+  PltEntrySize = 16;
+  PltHeaderSize = 20;
+  // ARM uses Variant 1 TLS
+  TcbSize = 8;
+  NeedsThunks = true;
+}
+
+RelExpr ARM::getRelExpr(uint32_t Type, const SymbolBody &S,
+                        const uint8_t *Loc) const {
+  switch (Type) {
+  default:
+    return R_ABS;
+  case R_ARM_THM_JUMP11:
+    return R_PC;
+  case R_ARM_CALL:
+  case R_ARM_JUMP24:
+  case R_ARM_PC24:
+  case R_ARM_PLT32:
+  case R_ARM_PREL31:
+  case R_ARM_THM_JUMP19:
+  case R_ARM_THM_JUMP24:
+  case R_ARM_THM_CALL:
+    return R_PLT_PC;
+  case R_ARM_GOTOFF32:
+    // (S + A) - GOT_ORG
+    return R_GOTREL;
+  case R_ARM_GOT_BREL:
+    // GOT(S) + A - GOT_ORG
+    return R_GOT_OFF;
+  case R_ARM_GOT_PREL:
+  case R_ARM_TLS_IE32:
+    // GOT(S) + A - P
+    return R_GOT_PC;
+  case R_ARM_SBREL32:
+    return R_ARM_SBREL;
+  case R_ARM_TARGET1:
+    return Config->Target1Rel ? R_PC : R_ABS;
+  case R_ARM_TARGET2:
+    if (Config->Target2 == Target2Policy::Rel)
+      return R_PC;
+    if (Config->Target2 == Target2Policy::Abs)
+      return R_ABS;
+    return R_GOT_PC;
+  case R_ARM_TLS_GD32:
+    return R_TLSGD_PC;
+  case R_ARM_TLS_LDM32:
+    return R_TLSLD_PC;
+  case R_ARM_BASE_PREL:
+    // B(S) + A - P
+    // FIXME: currently B(S) assumed to be .got, this may not hold for all
+    // platforms.
+    return R_GOTONLY_PC;
+  case R_ARM_MOVW_PREL_NC:
+  case R_ARM_MOVT_PREL:
+  case R_ARM_REL32:
+  case R_ARM_THM_MOVW_PREL_NC:
+  case R_ARM_THM_MOVT_PREL:
+    return R_PC;
+  case R_ARM_NONE:
+    return R_NONE;
+  case R_ARM_TLS_LE32:
+    return R_TLS;
+  }
+}
+
+bool ARM::isPicRel(uint32_t Type) const {
+  return (Type == R_ARM_TARGET1 && !Config->Target1Rel) ||
+         (Type == R_ARM_ABS32);
+}
+
+uint32_t ARM::getDynRel(uint32_t Type) const {
+  if (Type == R_ARM_TARGET1 && !Config->Target1Rel)
+    return R_ARM_ABS32;
+  if (Type == R_ARM_ABS32)
+    return Type;
+  // Keep it going with a dummy value so that we can find more reloc errors.
+  return R_ARM_ABS32;
+}
+
+void ARM::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
+  write32le(Buf, InX::Plt->getVA());
+}
+
+void ARM::writeIgotPlt(uint8_t *Buf, const SymbolBody &S) const {
+  // An ARM entry is the address of the ifunc resolver function.
+  write32le(Buf, S.getVA());
+}
+
+void ARM::writePltHeader(uint8_t *Buf) const {
+  const uint8_t PltData[] = {
+      0x04, 0xe0, 0x2d, 0xe5, //     str lr, [sp,#-4]!
+      0x04, 0xe0, 0x9f, 0xe5, //     ldr lr, L2
+      0x0e, 0xe0, 0x8f, 0xe0, // L1: add lr, pc, lr
+      0x08, 0xf0, 0xbe, 0xe5, //     ldr pc, [lr, #8]
+      0x00, 0x00, 0x00, 0x00, // L2: .word   &(.got.plt) - L1 - 8
+  };
+  memcpy(Buf, PltData, sizeof(PltData));
+  uint64_t GotPlt = InX::GotPlt->getVA();
+  uint64_t L1 = InX::Plt->getVA() + 8;
+  write32le(Buf + 16, GotPlt - L1 - 8);
+}
+
+void ARM::addPltHeaderSymbols(InputSectionBase *ISD) const {
+  auto *IS = cast<InputSection>(ISD);
+  addSyntheticLocal("$a", STT_NOTYPE, 0, 0, IS);
+  addSyntheticLocal("$d", STT_NOTYPE, 16, 0, IS);
+}
+
+void ARM::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
+                   uint64_t PltEntryAddr, int32_t Index,
+                   unsigned RelOff) const {
+  // FIXME: Using simple code sequence with simple relocations.
+  // There is a more optimal sequence but it requires support for the group
+  // relocations. See ELF for the ARM Architecture Appendix A.3
+  const uint8_t PltData[] = {
+      0x04, 0xc0, 0x9f, 0xe5, //     ldr ip, L2
+      0x0f, 0xc0, 0x8c, 0xe0, // L1: add ip, ip, pc
+      0x00, 0xf0, 0x9c, 0xe5, //     ldr pc, [ip]
+      0x00, 0x00, 0x00, 0x00, // L2: .word   Offset(&(.plt.got) - L1 - 8
+  };
+  memcpy(Buf, PltData, sizeof(PltData));
+  uint64_t L1 = PltEntryAddr + 4;
+  write32le(Buf + 12, GotPltEntryAddr - L1 - 8);
+}
+
+void ARM::addPltSymbols(InputSectionBase *ISD, uint64_t Off) const {
+  auto *IS = cast<InputSection>(ISD);
+  addSyntheticLocal("$a", STT_NOTYPE, Off, 0, IS);
+  addSyntheticLocal("$d", STT_NOTYPE, Off + 12, 0, IS);
+}
+
+bool ARM::needsThunk(RelExpr Expr, uint32_t RelocType, const InputFile *File,
+                     const SymbolBody &S) const {
+  // If S is an undefined weak symbol in an executable we don't need a Thunk.
+  // In a DSO calls to undefined symbols, including weak ones get PLT entries
+  // which may need a thunk.
+  if (S.isUndefined() && !S.isLocal() && S.symbol()->isWeak() &&
+      !Config->Shared)
+    return false;
+  // A state change from ARM to Thumb and vice versa must go through an
+  // interworking thunk if the relocation type is not R_ARM_CALL or
+  // R_ARM_THM_CALL.
+  switch (RelocType) {
+  case R_ARM_PC24:
+  case R_ARM_PLT32:
+  case R_ARM_JUMP24:
+    // Source is ARM, all PLT entries are ARM so no interworking required.
+    // Otherwise we need to interwork if Symbol has bit 0 set (Thumb).
+    if (Expr == R_PC && ((S.getVA() & 1) == 1))
+      return true;
+    break;
+  case R_ARM_THM_JUMP19:
+  case R_ARM_THM_JUMP24:
+    // Source is Thumb, all PLT entries are ARM so interworking is required.
+    // Otherwise we need to interwork if Symbol has bit 0 clear (ARM).
+    if (Expr == R_PLT_PC || ((S.getVA() & 1) == 0))
+      return true;
+    break;
+  }
+  return false;
+}
+
+void ARM::relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const {
+  switch (Type) {
+  case R_ARM_ABS32:
+  case R_ARM_BASE_PREL:
+  case R_ARM_GLOB_DAT:
+  case R_ARM_GOTOFF32:
+  case R_ARM_GOT_BREL:
+  case R_ARM_GOT_PREL:
+  case R_ARM_REL32:
+  case R_ARM_RELATIVE:
+  case R_ARM_SBREL32:
+  case R_ARM_TARGET1:
+  case R_ARM_TARGET2:
+  case R_ARM_TLS_GD32:
+  case R_ARM_TLS_IE32:
+  case R_ARM_TLS_LDM32:
+  case R_ARM_TLS_LDO32:
+  case R_ARM_TLS_LE32:
+  case R_ARM_TLS_TPOFF32:
+  case R_ARM_TLS_DTPOFF32:
+    write32le(Loc, Val);
+    break;
+  case R_ARM_TLS_DTPMOD32:
+    write32le(Loc, 1);
+    break;
+  case R_ARM_PREL31:
+    checkInt<31>(Loc, Val, Type);
+    write32le(Loc, (read32le(Loc) & 0x80000000) | (Val & ~0x80000000));
+    break;
+  case R_ARM_CALL:
+    // R_ARM_CALL is used for BL and BLX instructions, depending on the
+    // value of bit 0 of Val, we must select a BL or BLX instruction
+    if (Val & 1) {
+      // If bit 0 of Val is 1 the target is Thumb, we must select a BLX.
+      // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1'
+      checkInt<26>(Loc, Val, Type);
+      write32le(Loc, 0xfa000000 |                    // opcode
+                         ((Val & 2) << 23) |         // H
+                         ((Val >> 2) & 0x00ffffff)); // imm24
+      break;
+    }
+    if ((read32le(Loc) & 0xfe000000) == 0xfa000000)
+      // BLX (always unconditional) instruction to an ARM Target, select an
+      // unconditional BL.
+      write32le(Loc, 0xeb000000 | (read32le(Loc) & 0x00ffffff));
+    // fall through as BL encoding is shared with B
+    LLVM_FALLTHROUGH;
+  case R_ARM_JUMP24:
+  case R_ARM_PC24:
+  case R_ARM_PLT32:
+    checkInt<26>(Loc, Val, Type);
+    write32le(Loc, (read32le(Loc) & ~0x00ffffff) | ((Val >> 2) & 0x00ffffff));
+    break;
+  case R_ARM_THM_JUMP11:
+    checkInt<12>(Loc, Val, Type);
+    write16le(Loc, (read32le(Loc) & 0xf800) | ((Val >> 1) & 0x07ff));
+    break;
+  case R_ARM_THM_JUMP19:
+    // Encoding T3: Val = S:J2:J1:imm6:imm11:0
+    checkInt<21>(Loc, Val, Type);
+    write16le(Loc,
+              (read16le(Loc) & 0xfbc0) |   // opcode cond
+                  ((Val >> 10) & 0x0400) | // S
+                  ((Val >> 12) & 0x003f)); // imm6
+    write16le(Loc + 2,
+              0x8000 |                    // opcode
+                  ((Val >> 8) & 0x0800) | // J2
+                  ((Val >> 5) & 0x2000) | // J1
+                  ((Val >> 1) & 0x07ff)); // imm11
+    break;
+  case R_ARM_THM_CALL:
+    // R_ARM_THM_CALL is used for BL and BLX instructions, depending on the
+    // value of bit 0 of Val, we must select a BL or BLX instruction
+    if ((Val & 1) == 0) {
+      // Ensure BLX destination is 4-byte aligned. As BLX instruction may
+      // only be two byte aligned. This must be done before overflow check
+      Val = alignTo(Val, 4);
+    }
+    // Bit 12 is 0 for BLX, 1 for BL
+    write16le(Loc + 2, (read16le(Loc + 2) & ~0x1000) | (Val & 1) << 12);
+    // Fall through as rest of encoding is the same as B.W
+    LLVM_FALLTHROUGH;
+  case R_ARM_THM_JUMP24:
+    // Encoding B  T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0
+    // FIXME: Use of I1 and I2 require v6T2ops
+    checkInt<25>(Loc, Val, Type);
+    write16le(Loc,
+              0xf000 |                     // opcode
+                  ((Val >> 14) & 0x0400) | // S
+                  ((Val >> 12) & 0x03ff)); // imm10
+    write16le(Loc + 2,
+              (read16le(Loc + 2) & 0xd000) |                  // opcode
+                  (((~(Val >> 10)) ^ (Val >> 11)) & 0x2000) | // J1
+                  (((~(Val >> 11)) ^ (Val >> 13)) & 0x0800) | // J2
+                  ((Val >> 1) & 0x07ff));                     // imm11
+    break;
+  case R_ARM_MOVW_ABS_NC:
+  case R_ARM_MOVW_PREL_NC:
+    write32le(Loc, (read32le(Loc) & ~0x000f0fff) | ((Val & 0xf000) << 4) |
+                       (Val & 0x0fff));
+    break;
+  case R_ARM_MOVT_ABS:
+  case R_ARM_MOVT_PREL:
+    checkInt<32>(Loc, Val, Type);
+    write32le(Loc, (read32le(Loc) & ~0x000f0fff) |
+                       (((Val >> 16) & 0xf000) << 4) | ((Val >> 16) & 0xfff));
+    break;
+  case R_ARM_THM_MOVT_ABS:
+  case R_ARM_THM_MOVT_PREL:
+    // Encoding T1: A = imm4:i:imm3:imm8
+    checkInt<32>(Loc, Val, Type);
+    write16le(Loc,
+              0xf2c0 |                     // opcode
+                  ((Val >> 17) & 0x0400) | // i
+                  ((Val >> 28) & 0x000f)); // imm4
+    write16le(Loc + 2,
+              (read16le(Loc + 2) & 0x8f00) | // opcode
+                  ((Val >> 12) & 0x7000) |   // imm3
+                  ((Val >> 16) & 0x00ff));   // imm8
+    break;
+  case R_ARM_THM_MOVW_ABS_NC:
+  case R_ARM_THM_MOVW_PREL_NC:
+    // Encoding T3: A = imm4:i:imm3:imm8
+    write16le(Loc,
+              0xf240 |                     // opcode
+                  ((Val >> 1) & 0x0400) |  // i
+                  ((Val >> 12) & 0x000f)); // imm4
+    write16le(Loc + 2,
+              (read16le(Loc + 2) & 0x8f00) | // opcode
+                  ((Val << 4) & 0x7000) |    // imm3
+                  (Val & 0x00ff));           // imm8
+    break;
+  default:
+    error(getErrorLocation(Loc) + "unrecognized reloc " + Twine(Type));
+  }
+}
+
+int64_t ARM::getImplicitAddend(const uint8_t *Buf, uint32_t Type) const {
+  switch (Type) {
+  default:
+    return 0;

*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***



Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201706162104.v5GL4E3H063811>