Date: Fri, 29 Apr 2011 00:00:54 +0000 (UTC) From: Jack F Vogel <jfv@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-8@freebsd.org Subject: svn commit: r221191 - in stable/8/sys/dev: e1000 ixgbe Message-ID: <201104290000.p3T00sNR074886@svn.freebsd.org>
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Author: jfv Date: Fri Apr 29 00:00:54 2011 New Revision: 221191 URL: http://svn.freebsd.org/changeset/base/221191 Log: MFC of the 1G Intel drivers, the following revisions from HEAD are merged: 217318,218530,218548,218581,218582,218583,218587,218588, 219753,219763,219764,220251,220254,220375,221187,221189 Modified: stable/8/sys/dev/e1000/e1000_80003es2lan.c stable/8/sys/dev/e1000/e1000_80003es2lan.h stable/8/sys/dev/e1000/e1000_82540.c stable/8/sys/dev/e1000/e1000_82541.c stable/8/sys/dev/e1000/e1000_82542.c stable/8/sys/dev/e1000/e1000_82543.c stable/8/sys/dev/e1000/e1000_82571.c stable/8/sys/dev/e1000/e1000_82575.c stable/8/sys/dev/e1000/e1000_82575.h stable/8/sys/dev/e1000/e1000_api.c stable/8/sys/dev/e1000/e1000_api.h stable/8/sys/dev/e1000/e1000_defines.h stable/8/sys/dev/e1000/e1000_hw.h stable/8/sys/dev/e1000/e1000_ich8lan.c stable/8/sys/dev/e1000/e1000_ich8lan.h stable/8/sys/dev/e1000/e1000_mac.c stable/8/sys/dev/e1000/e1000_mac.h stable/8/sys/dev/e1000/e1000_manage.c stable/8/sys/dev/e1000/e1000_manage.h stable/8/sys/dev/e1000/e1000_mbx.c stable/8/sys/dev/e1000/e1000_nvm.c stable/8/sys/dev/e1000/e1000_nvm.h stable/8/sys/dev/e1000/e1000_osdep.c stable/8/sys/dev/e1000/e1000_phy.c stable/8/sys/dev/e1000/e1000_phy.h stable/8/sys/dev/e1000/e1000_regs.h stable/8/sys/dev/e1000/e1000_vf.c stable/8/sys/dev/e1000/e1000_vf.h stable/8/sys/dev/e1000/if_em.c stable/8/sys/dev/e1000/if_em.h stable/8/sys/dev/e1000/if_igb.c stable/8/sys/dev/e1000/if_igb.h stable/8/sys/dev/e1000/if_lem.c stable/8/sys/dev/e1000/if_lem.h stable/8/sys/dev/ixgbe/ixgbe.c stable/8/sys/dev/ixgbe/ixgbe.h Directory Properties: stable/8/sys/ (props changed) stable/8/sys/amd64/include/xen/ (props changed) stable/8/sys/cddl/contrib/opensolaris/ (props changed) stable/8/sys/contrib/dev/acpica/ (props changed) stable/8/sys/contrib/pf/ (props changed) Modified: stable/8/sys/dev/e1000/e1000_80003es2lan.c ============================================================================== --- stable/8/sys/dev/e1000/e1000_80003es2lan.c Thu Apr 28 23:21:50 2011 (r221190) +++ stable/8/sys/dev/e1000/e1000_80003es2lan.c Fri Apr 29 00:00:54 2011 (r221191) @@ -82,8 +82,8 @@ static void e1000_power_down_phy_copper_ * with a lower bound at "index" and the upper bound at * "index + 5". */ -static const u16 e1000_gg82563_cable_length_table[] = - { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; +static const u16 e1000_gg82563_cable_length_table[] = { + 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; #define GG82563_CABLE_LENGTH_TABLE_SIZE \ (sizeof(e1000_gg82563_cable_length_table) / \ sizeof(e1000_gg82563_cable_length_table[0])) @@ -854,7 +854,7 @@ static s32 e1000_get_link_up_info_80003e **/ static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) { - u32 ctrl, icr; + u32 ctrl; s32 ret_val; DEBUGFUNC("e1000_reset_hw_80003es2lan"); @@ -890,7 +890,7 @@ static s32 e1000_reset_hw_80003es2lan(st /* Clear any pending interrupt events. */ E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); - icr = E1000_READ_REG(hw, E1000_ICR); + E1000_READ_REG(hw, E1000_ICR); ret_val = e1000_check_alt_mac_addr_generic(hw); @@ -909,6 +909,7 @@ static s32 e1000_init_hw_80003es2lan(str struct e1000_mac_info *mac = &hw->mac; u32 reg_data; s32 ret_val; + u16 kum_reg_data; u16 i; DEBUGFUNC("e1000_init_hw_80003es2lan"); @@ -936,6 +937,13 @@ static s32 e1000_init_hw_80003es2lan(str /* Setup link and flow control */ ret_val = mac->ops.setup_link(hw); + /* Disable IBIST slave mode (far-end loopback) */ + e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, + &kum_reg_data); + kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; + e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, + kum_reg_data); + /* Set the transmit descriptor write-back policy */ reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | Modified: stable/8/sys/dev/e1000/e1000_80003es2lan.h ============================================================================== --- stable/8/sys/dev/e1000/e1000_80003es2lan.h Thu Apr 28 23:21:50 2011 (r221190) +++ stable/8/sys/dev/e1000/e1000_80003es2lan.h Fri Apr 29 00:00:54 2011 (r221191) @@ -1,6 +1,6 @@ /****************************************************************************** - Copyright (c) 2001-2009, Intel Corporation + Copyright (c) 2001-2010, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without Modified: stable/8/sys/dev/e1000/e1000_82540.c ============================================================================== --- stable/8/sys/dev/e1000/e1000_82540.c Thu Apr 28 23:21:50 2011 (r221190) +++ stable/8/sys/dev/e1000/e1000_82540.c Fri Apr 29 00:00:54 2011 (r221191) @@ -269,7 +269,7 @@ void e1000_init_function_pointers_82540( **/ static s32 e1000_reset_hw_82540(struct e1000_hw *hw) { - u32 ctrl, icr, manc; + u32 ctrl, manc; s32 ret_val = E1000_SUCCESS; DEBUGFUNC("e1000_reset_hw_82540"); @@ -314,7 +314,7 @@ static s32 e1000_reset_hw_82540(struct e E1000_WRITE_REG(hw, E1000_MANC, manc); E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); - icr = E1000_READ_REG(hw, E1000_ICR); + E1000_READ_REG(hw, E1000_ICR); return ret_val; } Modified: stable/8/sys/dev/e1000/e1000_82541.c ============================================================================== --- stable/8/sys/dev/e1000/e1000_82541.c Thu Apr 28 23:21:50 2011 (r221190) +++ stable/8/sys/dev/e1000/e1000_82541.c Fri Apr 29 00:00:54 2011 (r221191) @@ -300,7 +300,7 @@ void e1000_init_function_pointers_82541( **/ static s32 e1000_reset_hw_82541(struct e1000_hw *hw) { - u32 ledctl, ctrl, icr, manc; + u32 ledctl, ctrl, manc; DEBUGFUNC("e1000_reset_hw_82541"); @@ -364,7 +364,7 @@ static s32 e1000_reset_hw_82541(struct e E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); /* Clear any pending interrupt events. */ - icr = E1000_READ_REG(hw, E1000_ICR); + E1000_READ_REG(hw, E1000_ICR); return E1000_SUCCESS; } @@ -390,7 +390,7 @@ static s32 e1000_init_hw_82541(struct e1 DEBUGOUT("Error initializing identification LED\n"); /* This is not fatal and we should not stop init due to this */ } - + /* Storing the Speed Power Down value for later use */ ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO, Modified: stable/8/sys/dev/e1000/e1000_82542.c ============================================================================== --- stable/8/sys/dev/e1000/e1000_82542.c Thu Apr 28 23:21:50 2011 (r221190) +++ stable/8/sys/dev/e1000/e1000_82542.c Fri Apr 29 00:00:54 2011 (r221191) @@ -51,7 +51,6 @@ static void e1000_rar_set_82542(struct e static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw); static s32 e1000_read_mac_addr_82542(struct e1000_hw *hw); - /** * e1000_init_phy_params_82542 - Init PHY func ptrs. * @hw: pointer to the HW structure @@ -192,7 +191,7 @@ static s32 e1000_reset_hw_82542(struct e { struct e1000_bus_info *bus = &hw->bus; s32 ret_val = E1000_SUCCESS; - u32 ctrl, icr; + u32 ctrl; DEBUGFUNC("e1000_reset_hw_82542"); @@ -223,7 +222,7 @@ static s32 e1000_reset_hw_82542(struct e msec_delay(2); E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); - icr = E1000_READ_REG(hw, E1000_ICR); + E1000_READ_REG(hw, E1000_ICR); if (hw->revision_id == E1000_REVISION_2) { if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) Modified: stable/8/sys/dev/e1000/e1000_82543.c ============================================================================== --- stable/8/sys/dev/e1000/e1000_82543.c Thu Apr 28 23:21:50 2011 (r221190) +++ stable/8/sys/dev/e1000/e1000_82543.c Fri Apr 29 00:00:54 2011 (r221191) @@ -901,7 +901,7 @@ static s32 e1000_phy_hw_reset_82543(stru **/ static s32 e1000_reset_hw_82543(struct e1000_hw *hw) { - u32 ctrl, icr; + u32 ctrl; s32 ret_val = E1000_SUCCESS; DEBUGFUNC("e1000_reset_hw_82543"); @@ -943,7 +943,7 @@ static s32 e1000_reset_hw_82543(struct e /* Masking off and clearing any pending interrupts */ E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); - icr = E1000_READ_REG(hw, E1000_ICR); + E1000_READ_REG(hw, E1000_ICR); return ret_val; } Modified: stable/8/sys/dev/e1000/e1000_82571.c ============================================================================== --- stable/8/sys/dev/e1000/e1000_82571.c Thu Apr 28 23:21:50 2011 (r221190) +++ stable/8/sys/dev/e1000/e1000_82571.c Fri Apr 29 00:00:54 2011 (r221191) @@ -82,6 +82,10 @@ static s32 e1000_get_hw_semaphore_82573 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw); static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw); static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw); +static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, + bool active); +static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, + bool active); static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); @@ -95,7 +99,6 @@ static void e1000_power_down_phy_copper_ static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) { struct e1000_phy_info *phy = &hw->phy; - struct e1000_dev_spec_82571 *dev_spec = &hw->dev_spec._82571; s32 ret_val = E1000_SUCCESS; DEBUGFUNC("e1000_init_phy_params_82571"); @@ -129,16 +132,6 @@ static s32 e1000_init_phy_params_82571(s phy->ops.write_reg = e1000_write_phy_reg_igp; phy->ops.acquire = e1000_get_hw_semaphore_82571; phy->ops.release = e1000_put_hw_semaphore_82571; - - /* This uses above function pointers */ - ret_val = e1000_get_phy_id_82571(hw); - - /* Verify PHY ID */ - if (phy->id != IGP01E1000_I_PHY_ID) { - ret_val = -E1000_ERR_PHY; - DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); - goto out; - } break; case e1000_82573: phy->type = e1000_phy_m88; @@ -152,20 +145,10 @@ static s32 e1000_init_phy_params_82571(s phy->ops.write_reg = e1000_write_phy_reg_m88; phy->ops.acquire = e1000_get_hw_semaphore_82571; phy->ops.release = e1000_put_hw_semaphore_82571; - - /* This uses above function pointers */ - ret_val = e1000_get_phy_id_82571(hw); - - /* Verify PHY ID */ - if (phy->id != M88E1111_I_PHY_ID) { - ret_val = -E1000_ERR_PHY; - DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); - goto out; - } break; case e1000_82574: case e1000_82583: - E1000_MUTEX_INIT(&dev_spec->swflag_mutex); + E1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex); phy->type = e1000_phy_bm; phy->ops.get_cfg_done = e1000_get_cfg_done_generic; @@ -178,22 +161,46 @@ static s32 e1000_init_phy_params_82571(s phy->ops.write_reg = e1000_write_phy_reg_bm2; phy->ops.acquire = e1000_get_hw_semaphore_82574; phy->ops.release = e1000_put_hw_semaphore_82574; + phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574; + phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574; + break; + default: + ret_val = -E1000_ERR_PHY; + goto out; + break; + } + + /* This can only be done after all function pointers are setup. */ + ret_val = e1000_get_phy_id_82571(hw); + if (ret_val) { + DEBUGOUT("Error getting PHY ID\n"); + goto out; + } - /* This uses above function pointers */ - ret_val = e1000_get_phy_id_82571(hw); - /* Verify PHY ID */ - if (phy->id != BME1000_E_PHY_ID_R2) { + /* Verify phy id */ + switch (hw->mac.type) { + case e1000_82571: + case e1000_82572: + if (phy->id != IGP01E1000_I_PHY_ID) + ret_val = -E1000_ERR_PHY; + break; + case e1000_82573: + if (phy->id != M88E1111_I_PHY_ID) + ret_val = -E1000_ERR_PHY; + break; + case e1000_82574: + case e1000_82583: + if (phy->id != BME1000_E_PHY_ID_R2) ret_val = -E1000_ERR_PHY; - DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); - goto out; - } break; default: ret_val = -E1000_ERR_PHY; - goto out; break; } + if (ret_val) + DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id); + out: return ret_val; } @@ -693,6 +700,62 @@ static void e1000_put_hw_semaphore_82574 } /** + * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state + * @hw: pointer to the HW structure + * @active: TRUE to enable LPLU, FALSE to disable + * + * Sets the LPLU D0 state according to the active flag. + * LPLU will not be activated unless the + * device autonegotiation advertisement meets standards of + * either 10 or 10/100 or 10/100/1000 at all duplexes. + * This is a function pointer entry point only called by + * PHY setup routines. + **/ +static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active) +{ + u16 data = E1000_READ_REG(hw, E1000_POEMB); + + DEBUGFUNC("e1000_set_d0_lplu_state_82574"); + + if (active) + data |= E1000_PHY_CTRL_D0A_LPLU; + else + data &= ~E1000_PHY_CTRL_D0A_LPLU; + + E1000_WRITE_REG(hw, E1000_POEMB, data); + return E1000_SUCCESS; +} + +/** + * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3 + * @hw: pointer to the HW structure + * @active: boolean used to enable/disable lplu + * + * The low power link up (lplu) state is set to the power management level D3 + * when active is TRUE, else clear lplu for D3. LPLU + * is used during Dx states where the power conservation is most important. + * During driver activity, SmartSpeed should be enabled so performance is + * maintained. + **/ +static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active) +{ + u16 data = E1000_READ_REG(hw, E1000_POEMB); + + DEBUGFUNC("e1000_set_d3_lplu_state_82574"); + + if (!active) { + data &= ~E1000_PHY_CTRL_NOND0A_LPLU; + } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || + (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) || + (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) { + data |= E1000_PHY_CTRL_NOND0A_LPLU; + } + + E1000_WRITE_REG(hw, E1000_POEMB, data); + return E1000_SUCCESS; +} + +/** * e1000_acquire_nvm_82571 - Request for access to the EEPROM * @hw: pointer to the HW structure * @@ -1039,7 +1102,7 @@ out: **/ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) { - u32 ctrl, ctrl_ext, icr; + u32 ctrl, ctrl_ext; s32 ret_val; DEBUGFUNC("e1000_reset_hw_82571"); @@ -1125,7 +1188,7 @@ static s32 e1000_reset_hw_82571(struct e /* Clear any pending interrupt events. */ E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); - icr = E1000_READ_REG(hw, E1000_ICR); + E1000_READ_REG(hw, E1000_ICR); if (hw->mac.type == e1000_82571) { /* Install any alternate MAC address into RAR0 */ @@ -1336,7 +1399,7 @@ static void e1000_initialize_hw_bits_825 * apply workaround for hardware errata documented in errata * docs Fixes issue where some error prone or unreliable PCIe * completions are occurring, particularly with ASPM enabled. - * Without fix, issue can cause tx timeouts. + * Without fix, issue can cause Tx timeouts. */ reg = E1000_READ_REG(hw, E1000_GCR2); reg |= 1; @@ -1467,7 +1530,7 @@ bool e1000_check_phy_82574(struct e1000_ &receive_errors); if (ret_val) goto out; - if (receive_errors == E1000_RECEIVE_ERROR_MAX) { + if (receive_errors == E1000_RECEIVE_ERROR_MAX) { ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS, &status_1kbt); if (ret_val) @@ -1510,6 +1573,7 @@ static s32 e1000_setup_link_82571(struct default: break; } + return e1000_setup_link_generic(hw); } @@ -1645,7 +1709,7 @@ static s32 e1000_check_for_serdes_link_8 * auto-negotiation in the TXCW register and disable * forced link in the Device Control register in an * attempt to auto-negotiate with our link partner. - * If the partner code word is null, stop forcing + * If the partner code word is null, stop forcing * and restart auto negotiation. */ if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW)) { Modified: stable/8/sys/dev/e1000/e1000_82575.c ============================================================================== --- stable/8/sys/dev/e1000/e1000_82575.c Thu Apr 28 23:21:50 2011 (r221190) +++ stable/8/sys/dev/e1000/e1000_82575.c Fri Apr 29 00:00:54 2011 (r221191) @@ -36,7 +36,6 @@ * 82575EB Gigabit Network Connection * 82575EB Gigabit Backplane Connection * 82575GB Gigabit Network Connection - * 82575GB Gigabit Network Connection * 82576 Gigabit Network Connection * 82576 Quad Port Gigabit Mezzanine Adapter */ @@ -44,7 +43,6 @@ #include "e1000_api.h" static s32 e1000_init_phy_params_82575(struct e1000_hw *hw); -static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw); static s32 e1000_init_mac_params_82575(struct e1000_hw *hw); static s32 e1000_acquire_phy_82575(struct e1000_hw *hw); static void e1000_release_phy_82575(struct e1000_hw *hw); @@ -60,10 +58,14 @@ static s32 e1000_read_phy_reg_sgmii_825 u16 *data); static s32 e1000_reset_hw_82575(struct e1000_hw *hw); static s32 e1000_reset_hw_82580(struct e1000_hw *hw); -static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, +static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data); -static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, +static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data); +static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, + bool active); +static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, + bool active); static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active); static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); @@ -86,6 +88,14 @@ static void e1000_shutdown_serdes_link_8 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw); static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw); static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw); +static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw); +static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw); +static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, + u16 offset); +static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, + u16 offset); +static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw); +static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw); static const u16 e1000_82580_rxpbs_table[] = { 36, 72, 144, 1, 2, 4, 8, 16, @@ -115,6 +125,7 @@ static bool e1000_sgmii_uses_mdio_82575( ext_mdio = !!(reg & E1000_MDIC_DEST); break; case e1000_82580: + case e1000_i350: reg = E1000_READ_REG(hw, E1000_MDICNFG); ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); break; @@ -165,7 +176,7 @@ static s32 e1000_init_phy_params_82575(s E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); e1000_reset_mdicnfg_82580(hw); - + if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) { phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; @@ -182,11 +193,19 @@ static s32 e1000_init_phy_params_82575(s /* Verify phy id and set remaining function pointers */ switch (phy->id) { + case I347AT4_E_PHY_ID: + case M88E1112_E_PHY_ID: + case M88E1340M_E_PHY_ID: case M88E1111_I_PHY_ID: phy->type = e1000_phy_m88; phy->ops.check_polarity = e1000_check_polarity_m88; phy->ops.get_info = e1000_get_phy_info_m88; - phy->ops.get_cable_length = e1000_get_cable_length_m88; + if (phy->id == I347AT4_E_PHY_ID || + phy->id == M88E1112_E_PHY_ID || + phy->id == M88E1340M_E_PHY_ID) + phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2; + else + phy->ops.get_cable_length = e1000_get_cable_length_m88; phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; break; case IGP03E1000_E_PHY_ID: @@ -200,11 +219,14 @@ static s32 e1000_init_phy_params_82575(s phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; break; case I82580_I_PHY_ID: + case I350_I_PHY_ID: phy->type = e1000_phy_82580; phy->ops.check_polarity = e1000_check_polarity_82577; phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82577; phy->ops.get_cable_length = e1000_get_cable_length_82577; phy->ops.get_info = e1000_get_phy_info_82577; + phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; + phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580; break; default: ret_val = -E1000_ERR_PHY; @@ -219,7 +241,7 @@ out: * e1000_init_nvm_params_82575 - Init NVM func ptrs. * @hw: pointer to the HW structure **/ -static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) +s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) { struct e1000_nvm_info *nvm = &hw->nvm; u32 eecd = E1000_READ_REG(hw, E1000_EECD); @@ -227,6 +249,15 @@ static s32 e1000_init_nvm_params_82575(s DEBUGFUNC("e1000_init_nvm_params_82575"); + size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> + E1000_EECD_SIZE_EX_SHIFT); + /* + * Added to a constant, "size" becomes the left-shift value + * for setting word_size. + */ + size += NVM_WORD_SIZE_BASE_SHIFT; + + nvm->word_size = 1 << size; nvm->opcode_bits = 8; nvm->delay_usec = 1; switch (nvm->override) { @@ -244,30 +275,37 @@ static s32 e1000_init_nvm_params_82575(s break; } - nvm->type = e1000_nvm_eeprom_spi; + nvm->type = e1000_nvm_eeprom_spi; - size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> - E1000_EECD_SIZE_EX_SHIFT); + if (nvm->word_size == (1 << 15)) + nvm->page_size = 128; - /* - * Added to a constant, "size" becomes the left-shift value - * for setting word_size. - */ - size += NVM_WORD_SIZE_BASE_SHIFT; + /* Function Pointers */ + nvm->ops.acquire = e1000_acquire_nvm_82575; + nvm->ops.release = e1000_release_nvm_82575; + if (nvm->word_size < (1 << 15)) + nvm->ops.read = e1000_read_nvm_eerd; + else + nvm->ops.read = e1000_read_nvm_spi; - /* EEPROM access above 16k is unsupported */ - if (size > 14) - size = 14; - nvm->word_size = 1 << size; + nvm->ops.write = e1000_write_nvm_spi; + nvm->ops.validate = e1000_validate_nvm_checksum_generic; + nvm->ops.update = e1000_update_nvm_checksum_generic; + nvm->ops.valid_led_default = e1000_valid_led_default_82575; - /* Function Pointers */ - nvm->ops.acquire = e1000_acquire_nvm_82575; - nvm->ops.read = e1000_read_nvm_eerd; - nvm->ops.release = e1000_release_nvm_82575; - nvm->ops.update = e1000_update_nvm_checksum_generic; - nvm->ops.valid_led_default = e1000_valid_led_default_82575; - nvm->ops.validate = e1000_validate_nvm_checksum_generic; - nvm->ops.write = e1000_write_nvm_spi; + /* override genric family function pointers for specific descendants */ + switch (hw->mac.type) { + case e1000_82580: + nvm->ops.validate = e1000_validate_nvm_checksum_82580; + nvm->ops.update = e1000_update_nvm_checksum_82580; + break; + case e1000_i350: + nvm->ops.validate = e1000_validate_nvm_checksum_i350; + nvm->ops.update = e1000_update_nvm_checksum_i350; + break; + default: + break; + } return E1000_SUCCESS; } @@ -318,6 +356,12 @@ static s32 e1000_init_mac_params_82575(s mac->rar_entry_count = E1000_RAR_ENTRIES_82576; if (mac->type == e1000_82580) mac->rar_entry_count = E1000_RAR_ENTRIES_82580; + if (mac->type == e1000_i350) { + mac->rar_entry_count = E1000_RAR_ENTRIES_I350; + /* Enable EEE default settings for i350 */ + dev_spec->eee_disable = FALSE; + } + /* Set if part includes ASF firmware */ mac->asf_firmware_present = TRUE; /* FWSM register */ @@ -550,6 +594,7 @@ static s32 e1000_get_phy_id_82575(struct phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; break; case e1000_82580: + case e1000_i350: mdic = E1000_READ_REG(hw, E1000_MDICNFG); mdic &= E1000_MDICNFG_PHY_MASK; phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; @@ -730,6 +775,103 @@ out: } /** + * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state + * @hw: pointer to the HW structure + * @active: TRUE to enable LPLU, FALSE to disable + * + * Sets the LPLU D0 state according to the active flag. When + * activating LPLU this function also disables smart speed + * and vice versa. LPLU will not be activated unless the + * device autonegotiation advertisement meets standards of + * either 10 or 10/100 or 10/100/1000 at all duplexes. + * This is a function pointer entry point only called by + * PHY setup routines. + **/ +static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val = E1000_SUCCESS; + u16 data; + + DEBUGFUNC("e1000_set_d0_lplu_state_82580"); + + data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); + + if (active) { + data |= E1000_82580_PM_D0_LPLU; + + /* When LPLU is enabled, we should disable SmartSpeed */ + data &= ~E1000_82580_PM_SPD; + } else { + data &= ~E1000_82580_PM_D0_LPLU; + + /* + * LPLU and SmartSpeed are mutually exclusive. LPLU is used + * during Dx states where the power conservation is most + * important. During driver activity we should enable + * SmartSpeed, so performance is maintained. + */ + if (phy->smart_speed == e1000_smart_speed_on) { + data |= E1000_82580_PM_SPD; + } else if (phy->smart_speed == e1000_smart_speed_off) { + data &= ~E1000_82580_PM_SPD; + } + } + + E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); + return ret_val; +} + +/** + * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3 + * @hw: pointer to the HW structure + * @active: boolean used to enable/disable lplu + * + * Success returns 0, Failure returns 1 + * + * The low power link up (lplu) state is set to the power management level D3 + * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 + * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU + * is used during Dx states where the power conservation is most important. + * During driver activity, SmartSpeed should be enabled so performance is + * maintained. + **/ +s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) +{ + struct e1000_phy_info *phy = &hw->phy; + s32 ret_val = E1000_SUCCESS; + u16 data; + + DEBUGFUNC("e1000_set_d3_lplu_state_82580"); + + data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); + + if (!active) { + data &= ~E1000_82580_PM_D3_LPLU; + /* + * LPLU and SmartSpeed are mutually exclusive. LPLU is used + * during Dx states where the power conservation is most + * important. During driver activity we should enable + * SmartSpeed, so performance is maintained. + */ + if (phy->smart_speed == e1000_smart_speed_on) { + data |= E1000_82580_PM_SPD; + } else if (phy->smart_speed == e1000_smart_speed_off) { + data &= ~E1000_82580_PM_SPD; + } + } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || + (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || + (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { + data |= E1000_82580_PM_D3_LPLU; + /* When LPLU is enabled, we should disable SmartSpeed */ + data &= ~E1000_82580_PM_SPD; + } + + E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); + return ret_val; +} + +/** * e1000_acquire_nvm_82575 - Request for access to EEPROM * @hw: pointer to the HW structure * @@ -747,9 +889,7 @@ static s32 e1000_acquire_nvm_82575(struc ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); if (ret_val) goto out; - ret_val = e1000_acquire_nvm_generic(hw); - if (ret_val) e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); @@ -768,7 +908,6 @@ static void e1000_release_nvm_82575(stru { DEBUGFUNC("e1000_release_nvm_82575"); - e1000_release_nvm_generic(hw); e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); } @@ -1076,7 +1215,7 @@ void e1000_shutdown_serdes_link_82575(st **/ static s32 e1000_reset_hw_82575(struct e1000_hw *hw) { - u32 ctrl, icr; + u32 ctrl; s32 ret_val; DEBUGFUNC("e1000_reset_hw_82575"); @@ -1126,7 +1265,7 @@ static s32 e1000_reset_hw_82575(struct e /* Clear any pending interrupt events. */ E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); - icr = E1000_READ_REG(hw, E1000_ICR); + E1000_READ_REG(hw, E1000_ICR); /* Install any alternate MAC address into RAR0 */ ret_val = e1000_check_alt_mac_addr_generic(hw); @@ -1222,7 +1361,12 @@ static s32 e1000_setup_copper_link_82575 } switch (hw->phy.type) { case e1000_phy_m88: - ret_val = e1000_copper_link_setup_m88(hw); + if (hw->phy.id == I347AT4_E_PHY_ID || + hw->phy.id == M88E1112_E_PHY_ID || + hw->phy.id == M88E1340M_E_PHY_ID) + ret_val = e1000_copper_link_setup_m88_gen2(hw); + else + ret_val = e1000_copper_link_setup_m88(hw); break; case e1000_phy_igp_3: ret_val = e1000_copper_link_setup_igp(hw); @@ -1570,7 +1714,7 @@ static void e1000_clear_hw_cntrs_82575(s } /** - * e1000_rx_fifo_flush_82575 - Clean rx fifo after RX enable + * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable * @hw: pointer to the HW structure * * After rx enable if managability is enabled then there is likely some @@ -1588,7 +1732,7 @@ void e1000_rx_fifo_flush_82575(struct e1 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) return; - /* Disable all RX queues */ + /* Disable all Rx queues */ for (i = 0; i < 4; i++) { rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); E1000_WRITE_REG(hw, E1000_RXDCTL(i), @@ -1626,7 +1770,7 @@ void e1000_rx_fifo_flush_82575(struct e1 E1000_WRITE_FLUSH(hw); msec_delay(2); - /* Enable RX queues that were previously enabled and restore our + /* Enable Rx queues that were previously enabled and restore our * previous state */ for (i = 0; i < 4; i++) @@ -1694,7 +1838,6 @@ out: return ret_val; } - /** * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing * @hw: pointer to the hardware struct @@ -1709,6 +1852,7 @@ void e1000_vmdq_set_anti_spoofing_pf(str switch (hw->mac.type) { case e1000_82576: + case e1000_i350: dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); if (enable) { dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK | @@ -1747,6 +1891,14 @@ void e1000_vmdq_set_loopback_pf(struct e dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); break; + case e1000_i350: + dtxswc = E1000_READ_REG(hw, E1000_TXSWC); + if (enable) + dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; + else + dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; + E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc); + break; default: /* Currently no other hardware supports loopback */ break; @@ -1831,7 +1983,7 @@ out: * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits * @hw: pointer to the HW structure * - * This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on + * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on * the values found in the EEPROM. This addresses an issue in which these * bits are not restored from EEPROM after reset. **/ @@ -1839,7 +1991,7 @@ static s32 e1000_reset_mdicnfg_82580(str { s32 ret_val = E1000_SUCCESS; u32 mdicnfg; - u16 nvm_data; + u16 nvm_data = 0; DEBUGFUNC("e1000_reset_mdicnfg_82580"); @@ -1878,7 +2030,7 @@ static s32 e1000_reset_hw_82580(struct e s32 ret_val = E1000_SUCCESS; /* BH SW mailbox bit in SW_FW_SYNC */ u16 swmbsw_mask = E1000_SW_SYNCH_MB; - u32 ctrl, icr; + u32 ctrl; bool global_device_reset = hw->dev_spec._82575.global_device_reset; DEBUGFUNC("e1000_reset_hw_82580"); @@ -1940,7 +2092,7 @@ static s32 e1000_reset_hw_82580(struct e /* Clear any pending interrupt events. */ E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); - icr = E1000_READ_REG(hw, E1000_ICR); + E1000_READ_REG(hw, E1000_ICR); ret_val = e1000_reset_mdicnfg_82580(hw); if (ret_val) @@ -1957,7 +2109,7 @@ static s32 e1000_reset_hw_82580(struct e } /** - * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size + * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size * @data: data received by reading RXPBS register * * The 82580 uses a table based approach for packet buffer allocation sizes. @@ -1975,3 +2127,263 @@ u16 e1000_rxpbs_adjust_82580(u32 data) return ret_val; } + +/** + * e1000_validate_nvm_checksum_with_offset - Validate EEPROM + * checksum + * @hw: pointer to the HW structure + * @offset: offset in words of the checksum protected region + * + * Calculates the EEPROM checksum by reading/adding each word of the EEPROM + * and then verifies that the sum of the EEPROM is equal to 0xBABA. + **/ +s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) +{ + s32 ret_val = E1000_SUCCESS; + u16 checksum = 0; + u16 i, nvm_data; + + DEBUGFUNC("e1000_validate_nvm_checksum_with_offset"); + + for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) { + ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); + if (ret_val) { + DEBUGOUT("NVM Read Error\n"); + goto out; + } + checksum += nvm_data; + } + + if (checksum != (u16) NVM_SUM) { + DEBUGOUT("NVM Checksum Invalid\n"); + ret_val = -E1000_ERR_NVM; + goto out; + } + +out: + return ret_val; +} + +/** + * e1000_update_nvm_checksum_with_offset - Update EEPROM + * checksum + * @hw: pointer to the HW structure + * @offset: offset in words of the checksum protected region + * + * Updates the EEPROM checksum by reading/adding each word of the EEPROM + * up to the checksum. Then calculates the EEPROM checksum and writes the + * value to the EEPROM. + **/ +s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) +{ + s32 ret_val; + u16 checksum = 0; + u16 i, nvm_data; + + DEBUGFUNC("e1000_update_nvm_checksum_with_offset"); + + for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) { + ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); + if (ret_val) { + DEBUGOUT("NVM Read Error while updating checksum.\n"); + goto out; + } + checksum += nvm_data; + } + checksum = (u16) NVM_SUM - checksum; + ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, + &checksum); + if (ret_val) + DEBUGOUT("NVM Write Error while updating checksum.\n"); + +out: + return ret_val; +} + +/** + * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum + * @hw: pointer to the HW structure + * + * Calculates the EEPROM section checksum by reading/adding each word of + * the EEPROM and then verifies that the sum of the EEPROM is + * equal to 0xBABA. + **/ +static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw) +{ + s32 ret_val = E1000_SUCCESS; + u16 eeprom_regions_count = 1; + u16 j, nvm_data; + u16 nvm_offset; + + DEBUGFUNC("e1000_validate_nvm_checksum_82580"); + + ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); + if (ret_val) { + DEBUGOUT("NVM Read Error\n"); + goto out; + } + + if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) { + /* if chekcsums compatibility bit is set validate checksums + * for all 4 ports. */ + eeprom_regions_count = 4; + } + + for (j = 0; j < eeprom_regions_count; j++) { + nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); + ret_val = e1000_validate_nvm_checksum_with_offset(hw, + nvm_offset); + if (ret_val != E1000_SUCCESS) + goto out; + } + +out: + return ret_val; +} + +/** + * e1000_update_nvm_checksum_82580 - Update EEPROM checksum + * @hw: pointer to the HW structure + * + * Updates the EEPROM section checksums for all 4 ports by reading/adding + * each word of the EEPROM up to the checksum. Then calculates the EEPROM + * checksum and writes the value to the EEPROM. + **/ +static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw) +{ + s32 ret_val; + u16 j, nvm_data; + u16 nvm_offset; + + DEBUGFUNC("e1000_update_nvm_checksum_82580"); + + ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); + if (ret_val) { + DEBUGOUT("NVM Read Error while updating checksum" + " compatibility bit.\n"); + goto out; + } + + if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) { + /* set compatibility bit to validate checksums appropriately */ + nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK; + ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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