Date: Fri, 8 May 2020 15:05:05 +0000 (UTC) From: John Baldwin <jhb@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r360817 - stable/12/sys/riscv/riscv Message-ID: <202005081505.048F55WS075125@repo.freebsd.org>
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Author: jhb Date: Fri May 8 15:05:05 2020 New Revision: 360817 URL: https://svnweb.freebsd.org/changeset/base/360817 Log: MFC 354603,354604,354717,354718: Sync PLIC code with head. 354603: plic: fix PLIC_MAX_IRQS The maximum number of PLIC interrupts is defined in the PLIC spec[1] as 1024. 354604: plic: check for sifive compatible string The Linux dts for the HiFive Unleashed does not contain the usual "riscv,plic0" compat string, but our PLIC driver is compatible. 354717: plic: fix context calculation The RISC-V PLIC (platform level interrupt controller) registers are divided up by "context", which is purposefully left ambiguous in the PLIC spec. Currently we assume each CPU number corresponds 1-to-1 with a context number, but that is not correct. Most existing PLIC implementations (such as SiFive's) have multiple contexts per-cpu. For example, a single CPU might have a context for machine mode interrupts and a context for supervisor mode interrupts. To complicate things further, FreeBSD renumbers the CPUs during boot, but the PLIC driver still assumes that CPU ID equals the RISC-V hart number, meaning interrupt enables/claims might be performed for the wrong context registers. To fix this, we must calculate each CPU's context number during attachment. This is done by reading the interrupt properties from the device tree, from which a mapping from context to RISC-V hart to CPU number can be created. 354718: plic: support irq distribution Our PLIC implementation only enables interrupts on the boot cpu. Implement plic_bind_intr() so that they can be redistributed near the end of boot during intr_irq_shuffle(). This also slightly modifies how enable bits are handled in an attempt to better fit the PIC interface. plic_enable_intr()/plic_disable_intr() are converted to manage an interrupt source's threshold value, since this value can be used as to globally enable/disable an irq. All handing of the per-context enable bits is moved to the new methods plic_setup_intr() and plic_bind_intr(). Modified: stable/12/sys/riscv/riscv/plic.c Directory Properties: stable/12/ (props changed) Modified: stable/12/sys/riscv/riscv/plic.c ============================================================================== --- stable/12/sys/riscv/riscv/plic.c Fri May 8 15:03:28 2020 (r360816) +++ stable/12/sys/riscv/riscv/plic.c Fri May 8 15:05:05 2020 (r360817) @@ -3,11 +3,12 @@ * * Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com> * All rights reserved. + * Copyright (c) 2019 Mitchell Horne <mhorne@FreeBSD.org> * - * This software was developed by SRI International and the University of - * Cambridge Computer Laboratory (Department of Computer Science and - * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the - * DARPA SSITH research programme. + * Portions of this software were developed by SRI International and the + * University of Cambridge Computer Laboratory (Department of Computer Science + * and Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of + * the DARPA SSITH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -42,6 +43,7 @@ __FBSDID("$FreeBSD$"); #include <sys/module.h> #include <sys/proc.h> #include <sys/rman.h> +#include <sys/smp.h> #include <machine/bus.h> #include <machine/intr.h> @@ -52,21 +54,49 @@ __FBSDID("$FreeBSD$"); #include "pic_if.h" -#define PLIC_MAX_IRQS 2048 -#define PLIC_PRIORITY(n) (0x000000 + (n) * 0x4) -#define PLIC_ENABLE(n, h) (0x002000 + (h) * 0x80 + 4 * ((n) / 32)) -#define PLIC_THRESHOLD(h) (0x200000 + (h) * 0x1000 + 0x0) -#define PLIC_CLAIM(h) (0x200000 + (h) * 0x1000 + 0x4) +#define PLIC_MAX_IRQS 1024 +#define PLIC_PRIORITY_BASE 0x000000U + +#define PLIC_ENABLE_BASE 0x002000U +#define PLIC_ENABLE_STRIDE 0x80U + +#define PLIC_CONTEXT_BASE 0x200000U +#define PLIC_CONTEXT_STRIDE 0x1000U +#define PLIC_CONTEXT_THRESHOLD 0x0U +#define PLIC_CONTEXT_CLAIM 0x4U + +#define PLIC_PRIORITY(n) (PLIC_PRIORITY_BASE + (n) * sizeof(uint32_t)) +#define PLIC_ENABLE(sc, n, h) \ + (sc->contexts[h].enable_offset + ((n) / 32) * sizeof(uint32_t)) +#define PLIC_THRESHOLD(sc, h) \ + (sc->contexts[h].context_offset + PLIC_CONTEXT_THRESHOLD) +#define PLIC_CLAIM(sc, h) \ + (sc->contexts[h].context_offset + PLIC_CONTEXT_CLAIM) + +static pic_disable_intr_t plic_disable_intr; +static pic_enable_intr_t plic_enable_intr; +static pic_map_intr_t plic_map_intr; +static pic_setup_intr_t plic_setup_intr; +static pic_post_ithread_t plic_post_ithread; +static pic_pre_ithread_t plic_pre_ithread; +static pic_bind_intr_t plic_bind_intr; + struct plic_irqsrc { struct intr_irqsrc isrc; u_int irq; }; +struct plic_context { + bus_size_t enable_offset; + bus_size_t context_offset; +}; + struct plic_softc { device_t dev; struct resource * intc_res; struct plic_irqsrc isrcs[PLIC_MAX_IRQS]; + struct plic_context contexts[MAXCPU]; int ndev; }; @@ -75,6 +105,47 @@ struct plic_softc { #define WR4(sc, reg, val) \ bus_write_4(sc->intc_res, (reg), (val)) +static u_int plic_irq_cpu; + +static int +riscv_hartid_to_cpu(int hartid) +{ + int i; + + CPU_FOREACH(i) { + if (pcpu_find(i)->pc_hart == hartid) + return (i); + } + + return (-1); +} + +static int +plic_get_hartid(device_t dev, phandle_t intc) +{ + int hart; + + /* Check the interrupt controller layout. */ + if (OF_searchencprop(intc, "#interrupt-cells", &hart, + sizeof(hart)) == -1) { + device_printf(dev, + "Could not find #interrupt-cells for phandle %u\n", intc); + return (-1); + } + + /* + * The parent of the interrupt-controller is the CPU we are + * interested in, so search for its hart ID. + */ + if (OF_searchencprop(OF_parent(intc), "reg", (pcell_t *)&hart, + sizeof(hart)) == -1) { + device_printf(dev, "Could not find hartid\n"); + return (-1); + } + + return (hart); +} + static inline void plic_irq_dispatch(struct plic_softc *sc, u_int irq, struct trapframe *tf) @@ -98,11 +169,11 @@ plic_intr(void *arg) sc = arg; cpu = PCPU_GET(cpuid); - pending = RD4(sc, PLIC_CLAIM(cpu)); + pending = RD4(sc, PLIC_CLAIM(sc, cpu)); if (pending) { tf = curthread->td_intr_frame; plic_irq_dispatch(sc, pending, tf); - WR4(sc, PLIC_CLAIM(cpu), pending); + WR4(sc, PLIC_CLAIM(sc, cpu), pending); } return (FILTER_HANDLED); @@ -113,17 +184,11 @@ plic_disable_intr(device_t dev, struct intr_irqsrc *is { struct plic_softc *sc; struct plic_irqsrc *src; - uint32_t reg; - uint32_t cpu; sc = device_get_softc(dev); src = (struct plic_irqsrc *)isrc; - cpu = PCPU_GET(cpuid); - - reg = RD4(sc, PLIC_ENABLE(src->irq, cpu)); - reg &= ~(1 << (src->irq % 32)); - WR4(sc, PLIC_ENABLE(src->irq, cpu), reg); + WR4(sc, PLIC_PRIORITY(src->irq), 0); } static void @@ -131,19 +196,11 @@ plic_enable_intr(device_t dev, struct intr_irqsrc *isr { struct plic_softc *sc; struct plic_irqsrc *src; - uint32_t reg; - uint32_t cpu; sc = device_get_softc(dev); src = (struct plic_irqsrc *)isrc; WR4(sc, PLIC_PRIORITY(src->irq), 1); - - cpu = PCPU_GET(cpuid); - - reg = RD4(sc, PLIC_ENABLE(src->irq, cpu)); - reg |= (1 << (src->irq % 32)); - WR4(sc, PLIC_ENABLE(src->irq, cpu), reg); } static int @@ -174,7 +231,8 @@ plic_probe(device_t dev) if (!ofw_bus_status_okay(dev)) return (ENXIO); - if (!ofw_bus_is_compatible(dev, "riscv,plic0")) + if (!ofw_bus_is_compatible(dev, "riscv,plic0") && + !ofw_bus_is_compatible(dev, "sifive,plic-1.0.0")) return (ENXIO); device_set_desc(dev, "RISC-V PLIC"); @@ -188,6 +246,7 @@ plic_attach(device_t dev) struct plic_irqsrc *isrcs; struct plic_softc *sc; struct intr_pic *pic; + pcell_t *cells; uint32_t irq; const char *name; phandle_t node; @@ -195,6 +254,10 @@ plic_attach(device_t dev) uint32_t cpu; int error; int rid; + int nintr; + int context; + int i; + int hart; sc = device_get_softc(dev); @@ -224,9 +287,9 @@ plic_attach(device_t dev) return (ENXIO); } + /* Register the interrupt sources */ isrcs = sc->isrcs; name = device_get_nameunit(sc->dev); - cpu = PCPU_GET(cpuid); for (irq = 1; irq <= sc->ndev; irq++) { isrcs[irq].irq = irq; error = intr_isrc_register(&isrcs[irq].isrc, sc->dev, @@ -235,10 +298,72 @@ plic_attach(device_t dev) return (error); WR4(sc, PLIC_PRIORITY(irq), 0); - WR4(sc, PLIC_ENABLE(irq, cpu), 0); } - WR4(sc, PLIC_THRESHOLD(cpu), 0); + /* + * Calculate the per-cpu enable and context register offsets. + * + * This is tricky for a few reasons. The PLIC divides the interrupt + * enable, threshold, and claim bits by "context", where each context + * routes to a Core-Local Interrupt Controller (CLIC). + * + * The tricky part is that the PLIC spec imposes no restrictions on how + * these contexts are laid out. So for example, there is no guarantee + * that each CPU will have both a machine mode and supervisor context, + * or that different PLIC implementations will organize the context + * registers in the same way. On top of this, we must handle the fact + * that cpuid != hartid, as they may have been renumbered during boot. + * We perform the following steps: + * + * 1. Examine the PLIC's "interrupts-extended" property and skip any + * entries that are not for supervisor external interrupts. + * + * 2. Walk up the device tree to find the corresponding CPU, and grab + * it's hart ID. + * + * 3. Convert the hart to a cpuid, and calculate the register offsets + * based on the context number. + */ + nintr = OF_getencprop_alloc_multi(node, "interrupts-extended", + sizeof(uint32_t), (void **)&cells); + if (nintr <= 0) { + device_printf(dev, "Could not read interrupts-extended\n"); + return (ENXIO); + } + + /* interrupts-extended is a list of phandles and interrupt types. */ + for (i = 0, context = 0; i < nintr; i += 2, context++) { + /* Skip M-mode external interrupts */ + if (cells[i + 1] != IRQ_EXTERNAL_SUPERVISOR) + continue; + + /* Get the hart ID from the CLIC's phandle. */ + hart = plic_get_hartid(dev, OF_node_from_xref(cells[i])); + if (hart < 0) { + OF_prop_free(cells); + return (ENXIO); + } + + /* Get the corresponding cpuid. */ + cpu = riscv_hartid_to_cpu(hart); + if (cpu < 0) { + device_printf(dev, "Invalid hart!\n"); + OF_prop_free(cells); + return (ENXIO); + } + + /* Set the enable and context register offsets for the CPU. */ + sc->contexts[cpu].enable_offset = PLIC_ENABLE_BASE + + context * PLIC_ENABLE_STRIDE; + sc->contexts[cpu].context_offset = PLIC_CONTEXT_BASE + + context * PLIC_CONTEXT_STRIDE; + } + OF_prop_free(cells); + + /* Set the threshold for each CPU to accept all priorities. */ + CPU_FOREACH(cpu) + WR4(sc, PLIC_THRESHOLD(sc, cpu), 0); + xref = OF_xref_from_node(node); pic = intr_pic_register(sc->dev, xref); if (pic == NULL) @@ -252,25 +377,69 @@ plic_attach(device_t dev) static void plic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) { + + plic_disable_intr(dev, isrc); +} + +static void +plic_post_ithread(device_t dev, struct intr_irqsrc *isrc) +{ + + plic_enable_intr(dev, isrc); +} + +static int +plic_setup_intr(device_t dev, struct intr_irqsrc *isrc, + struct resource *res, struct intr_map_data *data) +{ struct plic_softc *sc; struct plic_irqsrc *src; sc = device_get_softc(dev); src = (struct plic_irqsrc *)isrc; - WR4(sc, PLIC_PRIORITY(src->irq), 0); + /* Bind to the boot CPU for now. */ + CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu); + plic_bind_intr(dev, isrc); + + return (0); } -static void -plic_post_ithread(device_t dev, struct intr_irqsrc *isrc) +static int +plic_bind_intr(device_t dev, struct intr_irqsrc *isrc) { struct plic_softc *sc; struct plic_irqsrc *src; + uint32_t reg; + u_int cpu; sc = device_get_softc(dev); src = (struct plic_irqsrc *)isrc; - WR4(sc, PLIC_PRIORITY(src->irq), 1); + /* Disable the interrupt source on all CPUs. */ + CPU_FOREACH(cpu) { + reg = RD4(sc, PLIC_ENABLE(sc, src->irq, cpu)); + reg &= ~(1 << (src->irq % 32)); + WR4(sc, PLIC_ENABLE(sc, src->irq, cpu), reg); + } + + if (CPU_EMPTY(&isrc->isrc_cpu)) { + cpu = plic_irq_cpu = intr_irq_next_cpu(plic_irq_cpu, &all_cpus); + CPU_SETOF(cpu, &isrc->isrc_cpu); + } else { + /* + * We will only bind to a single CPU so select the first + * CPU found. + */ + cpu = CPU_FFS(&isrc->isrc_cpu) - 1; + } + + /* Enable the interrupt on the selected CPU only. */ + reg = RD4(sc, PLIC_ENABLE(sc, src->irq, cpu)); + reg |= (1 << (src->irq % 32)); + WR4(sc, PLIC_ENABLE(sc, src->irq, cpu), reg); + + return (0); } static device_method_t plic_methods[] = { @@ -282,6 +451,8 @@ static device_method_t plic_methods[] = { DEVMETHOD(pic_map_intr, plic_map_intr), DEVMETHOD(pic_pre_ithread, plic_pre_ithread), DEVMETHOD(pic_post_ithread, plic_post_ithread), + DEVMETHOD(pic_setup_intr, plic_setup_intr), + DEVMETHOD(pic_bind_intr, plic_bind_intr), DEVMETHOD_END };
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