Date: Sat, 24 Sep 2016 07:55:49 +0000 (UTC) From: Andriy Gapon <avg@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r306290 - head/sys/dev/amdsbwd Message-ID: <201609240755.u8O7tn3K067554@repo.freebsd.org>
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Author: avg Date: Sat Sep 24 07:55:49 2016 New Revision: 306290 URL: https://svnweb.freebsd.org/changeset/base/306290 Log: clarify description of the 0x790b1022 / "KERNCZ"/ "CZ" device MFC after: 5 days X-MFC with: r306218 Modified: head/sys/dev/amdsbwd/amd_chipset.h Modified: head/sys/dev/amdsbwd/amd_chipset.h ============================================================================== --- head/sys/dev/amdsbwd/amd_chipset.h Sat Sep 24 07:09:43 2016 (r306289) +++ head/sys/dev/amdsbwd/amd_chipset.h Sat Sep 24 07:55:49 2016 (r306290) @@ -36,18 +36,23 @@ * At present there are three classes of supported chipsets: * - SB600 and S7x0 southbridges where the SMBus controller device has * a PCI Device ID of 0x43851002 and a revision less than 0x40 - * - SB8x0, SB9x0 southbridges and FCHs where the SMBus controller device has - * a PCI Device ID of 0x43851002 and a revision greater than or equal to 0x40 - * or the controller has an ID of 0x780b1022 and a revision less than 0x41 - * - FCHs where the SMBus controller device has a PCI Device ID of 0x780b1022 - * and a revision greater than or equal to 0x41 + * - several types of southbridges and FCHs: + * o SB8x0, SB9x0 southbridges where the SMBus controller device has a PCI + * Device ID of 0x43851002 and a revision greater than or equal to 0x40 + * o FCHs where the controller has an ID of 0x780b1022 and a revision less + * than 0x41 (various revisions of "Hudson" and "Bolton") + * o FCHs where the controller has an ID of 0x790b1022 and a revision less + * than 0x49 + * - several types of southbridges and FCHs: + * o FCHs where the SMBus controller device has a PCI Device ID of 0x780b1022 + * and a revision greater than or equal to 0x41 (integrated into "Mullins" + * processors, code named "ML") + * o FCHs where the controller has an ID of 0x790b1022 and a revision greater + * than or equal to 0x49 (integrated into "Carrizo" processors, code named + * "KERNCZ" or "CZ") + * * The register definitions are compatible within the classes and may be * incompatible accross them. - * So far there is no public documentation for "KERNCZ" FCH where the SMBus - * controller has a PCI ID of 0x790b1022. Based on some code in Linux it is - * assumed that revisions less than 0x49 are compatible with the SB8x0 class - * and revisions greater than or equal to 0x49 are compatible with the class - * of FCHs with 0x41+ revisions. */ /*
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