Date: Thu, 23 Jan 2014 02:10:30 +0000 (UTC) From: Justin Hibbits <jhibbits@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r261070 - projects/pmac_pmu/sys/powerpc/powermac Message-ID: <201401230210.s0N2AULH085512@svn.freebsd.org>
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Author: jhibbits Date: Thu Jan 23 02:10:30 2014 New Revision: 261070 URL: http://svnweb.freebsd.org/changeset/base/261070 Log: Add suspend/resume for Intrepid, Pangea, and Shasta Mac-IO chipsets. Also, fix a mis-merge. Modified: projects/pmac_pmu/sys/powerpc/powermac/macio.c projects/pmac_pmu/sys/powerpc/powermac/maciovar.h Modified: projects/pmac_pmu/sys/powerpc/powermac/macio.c ============================================================================== --- projects/pmac_pmu/sys/powerpc/powermac/macio.c Thu Jan 23 02:08:57 2014 (r261069) +++ projects/pmac_pmu/sys/powerpc/powermac/macio.c Thu Jan 23 02:10:30 2014 (r261070) @@ -71,7 +71,7 @@ struct macio_softc { struct resource *sc_memr; int sc_rev; int sc_devid; - uint32_t saved_fcrs[6]; + uint32_t saved_fcrs[11]; uint32_t saved_mbcr; }; @@ -665,11 +665,50 @@ macio_enable_wireless(device_t dev, bool static int macio_suspend(device_t dev) { - uint32_t temp; struct macio_softc *sc = device_get_softc(dev); + uint32_t temp; + uint32_t fcr_bits[3][2]; powerpc_sync(); + if (sc->sc_devid == 0x22) { + fcr_bits[0][0] = KEYLARGO_FCR0_SLEEP_SET; + fcr_bits[0][1] = KEYLARGO_FCR0_SLEEP_CLR; + fcr_bits[1][0] = KEYLARGO_FCR1_SLEEP_SET; + fcr_bits[1][1] = KEYLARGO_FCR1_SLEEP_CLR; + fcr_bits[2][0] = KEYLARGO_FCR2_SLEEP_SET; + fcr_bits[2][0] = KEYLARGO_FCR2_SLEEP_SET; + fcr_bits[3][1] = KEYLARGO_FCR3_SLEEP_CLR; + fcr_bits[3][1] = KEYLARGO_FCR3_SLEEP_CLR; + } else if (sc->sc_devid == 0x25) { + fcr_bits[0][0] = PANGEA_FCR0_SLEEP_SET; + fcr_bits[0][1] = PANGEA_FCR0_SLEEP_CLR; + fcr_bits[1][0] = PANGEA_FCR1_SLEEP_SET; + fcr_bits[1][1] = PANGEA_FCR1_SLEEP_CLR; + fcr_bits[2][0] = PANGEA_FCR2_SLEEP_SET; + fcr_bits[2][0] = PANGEA_FCR2_SLEEP_SET; + fcr_bits[3][1] = PANGEA_FCR3_SLEEP_CLR; + fcr_bits[3][1] = PANGEA_FCR3_SLEEP_CLR; + } else if (sc->sc_devid == 0x3e) { + fcr_bits[0][0] = INTREPID_FCR0_SLEEP_SET; + fcr_bits[0][1] = INTREPID_FCR0_SLEEP_CLR; + fcr_bits[1][0] = INTREPID_FCR1_SLEEP_SET; + fcr_bits[1][1] = INTREPID_FCR1_SLEEP_CLR; + fcr_bits[2][0] = INTREPID_FCR2_SLEEP_SET; + fcr_bits[2][0] = INTREPID_FCR2_SLEEP_SET; + fcr_bits[3][1] = INTREPID_FCR3_SLEEP_CLR; + fcr_bits[3][1] = INTREPID_FCR3_SLEEP_CLR; + } else if (sc->sc_devid == 0x4f) { + fcr_bits[0][0] = K2_FCR0_SLEEP_SET; + fcr_bits[0][1] = K2_FCR0_SLEEP_CLR; + fcr_bits[1][0] = K2_FCR1_SLEEP_SET; + fcr_bits[1][1] = K2_FCR1_SLEEP_CLR; + fcr_bits[2][0] = K2_FCR2_SLEEP_SET; + fcr_bits[2][0] = K2_FCR2_SLEEP_SET; + fcr_bits[3][1] = K2_FCR3_SLEEP_CLR; + fcr_bits[3][1] = K2_FCR3_SLEEP_CLR; + } + sc->saved_fcrs[0] = bus_read_4(sc->sc_memr, KEYLARGO_FCR0); sc->saved_fcrs[1] = bus_read_4(sc->sc_memr, KEYLARGO_FCR1); sc->saved_fcrs[2] = bus_read_4(sc->sc_memr, KEYLARGO_FCR2); @@ -677,16 +716,24 @@ static int macio_suspend(device_t dev) sc->saved_fcrs[4] = bus_read_4(sc->sc_memr, KEYLARGO_FCR4); sc->saved_fcrs[5] = bus_read_4(sc->sc_memr, KEYLARGO_FCR5); + if (sc->sc_devid == 0x4f) { + sc->saved_fcrs[6] = bus_read_4(sc->sc_memr, K2_FCR6); + sc->saved_fcrs[7] = bus_read_4(sc->sc_memr, K2_FCR7); + sc->saved_fcrs[8] = bus_read_4(sc->sc_memr, K2_FCR8); + sc->saved_fcrs[9] = bus_read_4(sc->sc_memr, K2_FCR9); + sc->saved_fcrs[10] = bus_read_4(sc->sc_memr, K2_FCR10); + } + temp = sc->saved_fcrs[0]; - temp |= FCR0_USB_REF_SUSPEND; - bus_write_4(sc->sc_memr, KEYLARGO_FCR0, temp); - eieio(); powerpc_sync(); - DELAY(1000); + if (sc->sc_devid == 0x22) { + temp |= FCR0_USB_REF_SUSPEND; + bus_write_4(sc->sc_memr, KEYLARGO_FCR0, temp); + eieio(); powerpc_sync(); + DELAY(1000); + } - temp &= ~(FCR0_SCCA_ENABLE | FCR0_SCCB_ENABLE | - FCR0_SCC_CELL_ENABLE | FCR0_IRDA_ENABLE | - FCR0_IRDA_CLK32_ENABLE | - FCR0_IRDA_CLK19_ENABLE); + temp |= fcr_bits[0][0]; + temp &= ~fcr_bits[0][1]; bus_write_4(sc->sc_memr, KEYLARGO_FCR0, temp); eieio(); powerpc_sync(); @@ -699,31 +746,21 @@ static int macio_suspend(device_t dev) } temp = sc->saved_fcrs[1]; - temp &= ~(FCR1_AUDIO_SEL_22MCLK | FCR1_AUDIO_CLK_ENABLE | - FCR1_AUDIO_CLKOUT_ENABLE | FCR1_AUDIO_CELL_ENABLE | - FCR1_I2S0_CELL_ENABLE | FCR1_I2S0_CLK_ENABLE | - FCR1_I2S0_ENABLE | - FCR1_I2S1_CELL_ENABLE | FCR1_I2S1_CLK_ENABLE | - FCR1_I2S1_ENABLE | - FCR1_EIDE0_ENABLE | FCR1_EIDE0_RESET | - FCR1_EIDE1_ENABLE | FCR1_EIDE1_RESET | - FCR1_UIDE_ENABLE - ); + temp |= fcr_bits[1][0]; + temp &= ~fcr_bits[1][1]; + bus_write_4(sc->sc_memr, KEYLARGO_FCR1, temp); eieio(); powerpc_sync(); temp = sc->saved_fcrs[2]; - temp &= ~FCR2_IOBUS_ENABLE; + temp |= fcr_bits[2][0]; + temp &= ~fcr_bits[2][1]; bus_write_4(sc->sc_memr, KEYLARGO_FCR2, temp); eieio(); powerpc_sync(); temp = sc->saved_fcrs[3]; - temp |= (FCR3_SHUTDOWN_PLL_KW6 | FCR3_SHUTDOWN_PLL_KW4 | - FCR3_SHUTDOWN_PLL_KW35 | FCR3_SHUTDOWN_PLL_KW12); - temp &= ~(FCR3_CLK_66_ENABLE | FCR3_CLK_49_ENABLE | - FCR3_CLK_45_ENABLE | FCR3_CLK_31_ENABLE | - FCR3_TMR_CLK18_ENABLE | FCR3_I2S1_CLK18_ENABLE | - FCR3_I2S0_CLK18_ENABLE | FCR3_VIA_CLK16_ENABLE); + temp |= fcr_bits[3][0]; + temp &= ~fcr_bits[3][1]; if (sc->sc_rev >= 2) temp |= (FCR3_SHUTDOWN_PLL_2X | FCR3_SHUTDOWN_PLL_TOTAL); bus_write_4(sc->sc_memr, KEYLARGO_FCR3, temp); @@ -746,6 +783,14 @@ static int macio_resume(device_t dev) bus_write_4(sc->sc_memr, KEYLARGO_FCR4, sc->saved_fcrs[4]); bus_write_4(sc->sc_memr, KEYLARGO_FCR5, sc->saved_fcrs[5]); + if (sc->sc_devid == 0x4f) { + bus_write_4(sc->sc_memr, K2_FCR6, sc->saved_fcrs[6]); + bus_write_4(sc->sc_memr, K2_FCR7, sc->saved_fcrs[7]); + bus_write_4(sc->sc_memr, K2_FCR8, sc->saved_fcrs[8]); + bus_write_4(sc->sc_memr, K2_FCR9, sc->saved_fcrs[9]); + bus_write_4(sc->sc_memr, K2_FCR10, sc->saved_fcrs[10]); + } + /* Let things settle. */ DELAY(1000); Modified: projects/pmac_pmu/sys/powerpc/powermac/maciovar.h ============================================================================== --- projects/pmac_pmu/sys/powerpc/powermac/maciovar.h Thu Jan 23 02:08:57 2014 (r261069) +++ projects/pmac_pmu/sys/powerpc/powermac/maciovar.h Thu Jan 23 02:10:30 2014 (r261070) @@ -78,63 +78,6 @@ #define FCR0_SCCA_ENABLE 0x00000010 #define FCR0_SCCB_ENABLE 0x00000020 #define FCR0_SCC_CELL_ENABLE 0x00000040 -#define FCR0_IRDA_ENABLE 0x00008000 -#define FCR0_IRDA_CLK32_ENABLE 0x00010000 -#define FCR0_IRDA_CLK19_ENABLE 0x00020000 - -#define FCR0_USB_REF_SUSPEND 0x10000000 - -#define FCR1_AUDIO_SEL_22MCLK 0x00000002 -#define FCR1_AUDIO_CLK_ENABLE 0x00000008 -#define FCR1_AUDIO_CLKOUT_ENABLE 0x00000020 -#define FCR1_AUDIO_CELL_ENABLE 0x00000040 -#define FCR1_I2S0_CELL_ENABLE 0x00000400 -#define FCR1_I2S0_CLK_ENABLE 0x00001000 -#define FCR1_I2S0_ENABLE 0x00002000 -#define FCR1_I2S1_CELL_ENABLE 0x00020000 -#define FCR1_I2S1_CLK_ENABLE 0x00080000 -#define FCR1_I2S1_ENABLE 0x00100000 -#define FCR1_EIDE0_ENABLE 0x00800000 -#define FCR1_EIDE0_RESET 0x01000000 -#define FCR1_EIDE1_ENABLE 0x04000000 -#define FCR1_EIDE1_RESET 0x08000000 -#define FCR1_UIDE_ENABLE 0x20000000 -#define FCR1_UIDE_RESET 0x40000000 - -#define FCR2_IOBUS_ENABLE 0x00000002 - -#define FCR3_SHUTDOWN_PLL_TOTAL 0x00000001 -#define FCR3_SHUTDOWN_PLL_KW6 0x00000002 -#define FCR3_SHUTDOWN_PLL_KW4 0x00000004 -#define FCR3_SHUTDOWN_PLL_KW35 0x00000008 -#define FCR3_SHUTDOWN_PLL_KW12 0x00000010 -#define FCR3_SHUTDOWN_PLL_2X 0x00000080 -#define FCR3_CLK_66_ENABLE 0x00000100 -#define FCR3_CLK_49_ENABLE 0x00000200 -#define FCR3_CLK_45_ENABLE 0x00000400 -#define FCR3_CLK_31_ENABLE 0x00000800 -#define FCR3_TMR_CLK18_ENABLE 0x00001000 -#define FCR3_I2S1_CLK18_ENABLE 0x00002000 -#define FCR3_I2S0_CLK18_ENABLE 0x00004000 -#define FCR3_VIA_CLK16_ENABLE 0x00008000 - -#define KEYLARGO_MEDIABAY 0x34 -#define KEYLARGO_MB0_DEV_ENABLE 0x00001000 -#define KEYLARGO_MB0_DEV_POWER 0x00000400 -#define KEYLARGO_MB0_DEV_RESET 0x00000200 -#define KEYLARGO_MB0_ENABLE 0x00000100 -#define KEYLARGO_MB1_DEV_ENABLE 0x10000000 -#define KEYLARGO_MB1_DEV_POWER 0x04000000 -#define KEYLARGO_MB1_DEV_RESET 0x02000000 -#define KEYLARGO_MB1_ENABLE 0x01000000 - -#define FCR0_CHOOSE_SCCB 0x00000001 -#define FCR0_CHOOSE_SCCA 0x00000002 -#define FCR0_SLOW_SCC_PCLK 0x00000004 -#define FCR0_RESET_SCC 0x00000008 -#define FCR0_SCCA_ENABLE 0x00000010 -#define FCR0_SCCB_ENABLE 0x00000020 -#define FCR0_SCC_CELL_ENABLE 0x00000040 #define FCR0_CHOOSE_VIA 0x00000080 #define FCR0_HIGH_BAND_FOR_1MB 0x00000080 #define FCR0_USE_IR_SOURCE_2 0x00000200 /* KeyLargo */ @@ -268,6 +211,70 @@ #define FCR5_CLK3_68_ENABLE 0x00000010 #define FCR5_CLK32_ENABLE 0x00000020 +/* KeyLargo sleep bits */ +#define KEYLARGO_FCR0_SLEEP_SET FCR0_USB_REF_SUSPEND +#define KEYLARGO_FCR0_SLEEP_CLR (FCR0_SCCA_ENABLE | FCR0_SCCB_ENABLE | \ + FCR0_SCC_CELL_ENABLE | FCR0_IRDA_ENABLE | FCR0_IRDA_CLK32_ENABLE | \ + FCR0_IRDA_CLK19_ENABLE) + +#define KEYLARGO_FCR1_SLEEP_SET 0 +#define KEYLARGO_FCR1_SLEEP_CLR (FCR1_AUDIO_SEL_22MCLK | FCR1_AUDIO_CLK_ENABLE | \ + FCR1_AUDIO_CLKOUT_ENABLE | FCR1_AUDIO_CELL_ENABLE | \ + FCR1_I2S0_CELL_ENABLE | FCR1_I2S0_CLK_ENABLE | FCR1_I2S0_ENABLE | \ + FCR1_I2S1_CELL_ENABLE | FCR1_I2S1_CLK_ENABLE | FCR1_I2S1_ENABLE | \ + FCR1_EIDE0_ENABLE | FCR1_EIDE1_ENABLE | FCR1_UIDE_ENABLE | \ + FCR1_EIDE0_RESET | FCR1_EIDE1_RESET) + +#define KEYLARGO_FCR2_SLEEP_SET 0 +#define KEYLARGO_FCR2_SLEEP_CLR FCR2_IOBUS_ENABLE + +#define KEYLARGO_FCR3_SLEEP_SET (FCR3_SHUTDOWN_PLL_KW6 | FCR3_SHUTDOWN_PLL_KW4 | \ + FCR3_SHUTDOWN_PLL_KW35 | FCR3_SHUTDOWN_PLL_KW12) +#define KEYLARGO_FCR3_SLEEP_CLR (FCR3_CLK_66_ENABLE | FCR3_CLK_49_ENABLE | \ + FCR3_CLK_45_ENABLE | FCR3_CLK_31_ENABLE | FCR3_TMR_CLK18_ENABLE | \ + FCR3_I2S1_CLK18_ENABLE | FCR3_I2S0_CLK18_ENABLE | FCR3_VIA_CLK32_ENABLE) + +/* Pangea sleep bits */ +#define PANGEA_FCR0_SLEEP_SET 0 +#define PANGEA_FCR0_SLEEP_CLR (FCR0_USB1_CELL_ENABLE | FCR0_USB0_CELL_ENABLE | \ + FCR0_SCC_CELL_ENABLE | FCR0_SCCB_ENABLE | FCR0_SCCA_ENABLE) + +#define PANGEA_FCR1_SLEEP_SET 0 +#define PANGEA_FCR1_SLEEP_CLR (FCR1_AUDIO_SEL_22MCLK | FCR1_AUDIO_CLK_ENABLE | \ + FCR1_AUDIO_CLKOUT_ENABLE | FCR1_AUDIO_CELL_ENABLE | \ + FCR1_I2S0_CELL_ENABLE | FCR1_I2S0_CLK_ENABLE | FCR1_I2S0_ENABLE | \ + FCR1_I2S1_CELL_ENABLE | FCR1_I2S1_CLK_ENABLE | FCR1_I2S1_ENABLE | \ + FCR1_UIDE_ENABLE) + +#define PANGEA_FCR2_SLEEP_SET FCR2_ALT_DATA_OUT +#define PANGEA_FCR2_SLEEP_CLR 0 + +#define PANGEEA_FCR3_SLEEP_SET (FCR3_SHUTDOWN_PLL_KW35 | \ + FCR3_SHUTDOWN_PLL_KW4 | FCR3_SHUTDOWN_PLL_KW6) +#define PANGEA_FCR3_SLEEP_CLR (FCR3_CLK_49_ENABLE | FCR3_CLK_45_ENABLE | \ + FCR3_CLK_31_ENABLE | FCR3_TMR_CLK18_ENABLE | \ + FCR3_I2S1_CLK18_ENABLE | FCR3_I2S0_CLK18_ENABLE | FCR3_VIA_CLK16_ENABLE) + +/* Intrepid sleep bits */ +#define INTREPID_FCR0_SLEEP_SET 0 +#define INTREPID_FCR0_SLEEP_CLR (FCR0_SCCA_ENABLE | FCR0_SCCB_ENABLE | \ + FCR0_SCC_CELL_ENABLE) + +#define INTREPID_FCR1_SLEEP_SET 0 +#define INTREPID_FCR1_SLEEP_CLR ( FCR1_I2S0_CELL_ENABLE | \ + FCR1_I2S0_CLK_ENABLE | FCR1_I2S0_ENABLE | \ + FCR1_I2S1_CELL_ENABLE | FCR1_I2S1_CLK_ENABLE | \ + FCR1_I2S1_ENABLE | FCR1_UIDE_ENABLE) + +#define INTREPID_FCR2_SLEEP_SET 0 +#define INTREPID_FCR2_SLEEP_CLR 0 + +#define INTREPID_FCR3_SLEEP_SET 0 +#define INTREPID_FCR3_SLEEP_CLR (FCR3_CLK_49_ENABLE | FCR3_CLK_45_ENABLE | \ + FCR3_TMR_CLK18_ENABLE | \ + FCR3_I2S1_CLK18_ENABLE | FCR3_I2S0_CLK18_ENABLE | FCR3_VIA_CLK16_ENABLE) + + /* * K2 FCRs. */ @@ -342,6 +349,23 @@ #define FCR9_K2_CLK49_IS_STOPPED 0x00001000 #define FCR9_K2_OSC25_SHUTDOWN 0x00008000 +/* K2 sleep bits */ +#define K2_FCR0_SLEEP_SET 0 +#define K2_FCR0_SLEEP_CLR (FCR0_USB1_CELL_ENABLE | FCR0_USB0_CELL_ENABLE | \ + FCR0_SCC_CELL_ENABLE | FCR0_SCCB_ENABLE | FCR0_SCCA_ENABLE) + +#define K2_FCR1_SLEEP_SET 0 +#define K2_FCR1_SLEEP_CLR ( FCR1_I2S0_CELL_ENABLE | \ + FCR1_I2S0_CLK_ENABLE | FCR1_I2S0_ENABLE | \ + FCR1_I2S1_CELL_ENABLE | FCR1_I2S1_CLK_ENABLE | FCR1_I2S1_ENABLE | \ + FCR1_K2_SATA_RESET | FCR1_K2_UATA_RESET | FCR1_K2_GB_CLK_ENABLE) + +#define K2_FCR2_SLEEP_SET 0 +#define K2_FCR2_SLEEP_CLR FCR2_K2_SB_MPIC_ENABLE_OUTPUTS + +#define K2_FCR3_SLEEP_SET 0 +#define K2_FCR3_SLEEP_CLR FCR3_K2_ENABLE_OSC25_SHUTDOWN + /* * Format of a macio reg property entry. */
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