Date: Wed, 14 Apr 2010 16:23:05 +0200 From: Rafal Jaworowski <raj@semihalf.com> To: John Baldwin <jhb@freebsd.org> Cc: Perforce Change Reviews <perforce@freebsd.org> Subject: Re: PERFORCE change 176892 for review Message-ID: <8607B86F-49F4-464D-9298-679A8B94A28C@semihalf.com> In-Reply-To: <201004140946.56425.jhb@freebsd.org> References: <201004141124.o3EBO4CI013888@repoman.freebsd.org> <201004140909.07013.jhb@freebsd.org> <8198D10C-668B-40B4-8F3E-2022DDEE969C@semihalf.com> <201004140946.56425.jhb@freebsd.org>
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On 2010-04-14, at 15:46, John Baldwin wrote: > On Wednesday 14 April 2010 9:38:19 am Rafal Jaworowski wrote: >> >> On 2010-04-14, at 15:09, John Baldwin wrote: >> >>> On Wednesday 14 April 2010 7:24:04 am Rafal Jaworowski wrote: >>>> http://p4web.freebsd.org/@@176892?ac=10 >>>> >>>> Change 176892 by raj@raj_fdt on 2010/04/14 11:23:50 >>>> >>>> Clean up PCI-Express regs definitions and usage. >>>> >>>> LTSSM is MPC85XX PCI-E specific, so make it local to the pcib back-end >>>> driver. >>>> >>>> Pointed out by: jhb >>>> >>>> Affected files ... >>>> >>>> .. //depot/projects/fdt/sys/dev/pci/pcireg.h#4 edit >>>> .. //depot/projects/fdt/sys/powerpc/mpc85xx/pci_fdt.c#4 edit >>>> >>>> Differences ... >>>> >>>> ==== //depot/projects/fdt/sys/dev/pci/pcireg.h#4 (text+ko) ==== >>>> >>>> @@ -218,17 +218,6 @@ >>>> >>>> #define PCIR_PCCARDIF_2 0x44 >>>> >>>> - >>>> -/* PCIE registers */ >>>> -#define PCIR_DCR 0x54 >>>> -#define PCIM_DCR_URR 0x0008 >>>> -#define PCIM_DCR_FER 0x0004 >>>> -#define PCIM_DCR_NFER 0x0002 >>>> -#define PCIR_DSR 0x56 >>>> -#define PCIR_LTSSM 0x404 >>>> -#define PCIM_LTSSM_L0 0x16 >>>> - >>>> - >>>> /* PCI device class, subclass and programming interface definitions */ >>>> >>>> #define PCIC_OLD 0x00 >>>> @@ -616,6 +605,9 @@ >>>> #define PCIR_EXPRESS_DEVICE_CAP 0x4 >>>> #define PCIM_EXP_CAP_MAX_PAYLOAD 0x0007 >>>> #define PCIR_EXPRESS_DEVICE_CTL 0x8 >>>> +#define PCIM_EXP_CTL_NFER_ENABLE 0x0002 >>>> +#define PCIM_EXP_CTL_FER_ENABLE 0x0004 >>>> +#define PCIM_EXP_CTL_URR_ENABLE 0x0008 >>>> #define PCIM_EXP_CTL_RELAXED_ORD_ENABLE 0x0010 >>>> #define PCIM_EXP_CTL_MAX_PAYLOAD 0x00e0 >>>> #define PCIM_EXP_CTL_NOSNOOP_ENABLE 0x0800 >>>> >>>> ==== //depot/projects/fdt/sys/powerpc/mpc85xx/pci_fdt.c#4 (text+ko) ==== >>>> >>>> @@ -90,6 +90,9 @@ >>>> #define REG_PEX_ERR_DR 0x0e00 >>>> #define REG_PEX_ERR_EN 0x0e08 >>>> >>>> +#define PCIR_LTSSM 0x404 >>>> +#define LTSSM_STAT_L0 0x16 >>> >>> I suspect that this is a PCI-e extended capability which we should > properly >>> support. I screwed up the name of pci_find_extcap(). It should probably > be >>> renamed to 'pci_find_cap()' and a new 'pci_find_extcap()' that handles > PCI-e >>> extended capabilities (which start at 0x400) should be added. >> >> It doesn't look like. I was looking at pci_find_extcap() in the hope of > reusing the mechanism. The LTSSM one does not comply with PCI-E extended > capabilities format i.e. it doesn have the "header" with capid / nextcap, so > cannot be found in the extended cap chain starting at 0x100. It just sticks at > 0x404 offset: > > Oh, bah, my bad. I had thought that the extended caps started at 0x400 rather > than 0x100. :) The config space of this controller is kinda messy wrt to PCI-E extended capabilities, undocumented at least. There is just one entry for advanced error reporting feature at 0x100, with all header content in place (with null next entry), but there's also a range starting at 0x400 called "internal", but nothing is documented besides the single reg at 0x404 out of the blue. Rafalhome | help
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