Date: Thu, 26 Sep 2019 01:54:25 +0000 (UTC) From: Warner Losh <imp@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r352735 - in stable/12/sys/dev: mpr mpr/mpi mps Message-ID: <201909260154.x8Q1sPGv069643@repo.freebsd.org>
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Author: imp Date: Thu Sep 26 01:54:24 2019 New Revision: 352735 URL: https://svnweb.freebsd.org/changeset/base/352735 Log: Catch up with stability fixes to mpr/mps in -current since 12 was branched. MFC r341755,r342354,r342355,r342386,r342387,r342388,r342526,r342528, r342530,r342531,r342533,r342534,r342535,r342536,r342659,r345479, r345485,r345573,r347237,r349849,r349909: r341755: Copy and clear the reply descriptor atomically. This prevents concurrency in the interrupt handlers (usually due to timeout/error recovery) from seeing and processing the same descriptor twice. r342354: mps(4), mpr(4): Fix lifetime of command buffer for mp?sas_get_sata_identify r342355: mps(4), mpr(4): remove SATA ID command cancellation hack r342386: First step in refactoring and fixing the error recovery and task management code in the mpr and mps drivers. Eliminate duplicated code and fix some comments. r342387: Commands for user-initated device resets should come from the high-priority allocator. Prior to this change, they would leak from the normal allocator. r342388: Further refactoring for task management commands. Also fix a related typo from the previous commit. r342526: Update MPI header files version to 2.00.52 from 2.00.48 r342528: Copy back the Sense data at proper location expected by the application r342530: Added support for NVMe Task Management r342531: Add Sea,Aero adapter support r342533: Enable atomic type descriptor support only for Sea & Aero cards r342534: On Aero/Sea A0 cards retry MPT Fusion registers reads for max three times r342535: Update copyright information r342536: Update mpr driver version to v23.00.00.00-fbsd r342659: Fix whitespace from r342528 r345479: r329522 created problemss with commands that enter the TIMEDOUT state but are successfully returned by the card (usually due to an abort being issued as part of timeout recovery). Remove what amounts to an insufficient KASSERT, and don't overwrite the state value. State should probably be re-designed, and that will be done with a future commit. r345485: Add event table decoding for SAS Broadcast Primitive events. r345573: Add missing break statements. Coverity CID 1400446. r347237: Add missing newline to debug printf. r349849: Fix bugs in recovery path and improve cm tracking r349909: More fully implement the state machine. Sponsored by: Netflix, Inc Modified: stable/12/sys/dev/mpr/mpi/mpi2.h stable/12/sys/dev/mpr/mpi/mpi2_cnfg.h stable/12/sys/dev/mpr/mpi/mpi2_hbd.h stable/12/sys/dev/mpr/mpi/mpi2_history.txt stable/12/sys/dev/mpr/mpi/mpi2_init.h stable/12/sys/dev/mpr/mpi/mpi2_ioc.h stable/12/sys/dev/mpr/mpi/mpi2_pci.h stable/12/sys/dev/mpr/mpi/mpi2_ra.h stable/12/sys/dev/mpr/mpi/mpi2_raid.h stable/12/sys/dev/mpr/mpi/mpi2_sas.h stable/12/sys/dev/mpr/mpi/mpi2_targ.h stable/12/sys/dev/mpr/mpi/mpi2_tool.h stable/12/sys/dev/mpr/mpi/mpi2_type.h stable/12/sys/dev/mpr/mpr.c stable/12/sys/dev/mpr/mpr_config.c stable/12/sys/dev/mpr/mpr_ioctl.h stable/12/sys/dev/mpr/mpr_mapping.c stable/12/sys/dev/mpr/mpr_mapping.h stable/12/sys/dev/mpr/mpr_pci.c stable/12/sys/dev/mpr/mpr_sas.c stable/12/sys/dev/mpr/mpr_sas.h stable/12/sys/dev/mpr/mpr_sas_lsi.c stable/12/sys/dev/mpr/mpr_table.c stable/12/sys/dev/mpr/mpr_user.c stable/12/sys/dev/mpr/mprvar.h stable/12/sys/dev/mps/mps.c stable/12/sys/dev/mps/mps_sas.c stable/12/sys/dev/mps/mps_sas_lsi.c stable/12/sys/dev/mps/mps_table.c stable/12/sys/dev/mps/mps_user.c stable/12/sys/dev/mps/mpsvar.h Directory Properties: stable/12/ (props changed) Modified: stable/12/sys/dev/mpr/mpi/mpi2.h ============================================================================== --- stable/12/sys/dev/mpr/mpi/mpi2.h Thu Sep 26 01:51:55 2019 (r352734) +++ stable/12/sys/dev/mpr/mpi/mpi2.h Thu Sep 26 01:54:24 2019 (r352735) @@ -1,7 +1,5 @@ /*- - * Copyright (c) 2012-2015 LSI Corp. - * Copyright (c) 2013-2016 Avago Technologies - * All rights reserved. + * Copyright 2000-2020 Broadcom Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -27,15 +25,13 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD + * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD * * $FreeBSD$ */ /* - * Copyright (c) 2000-2015 LSI Corporation. - * Copyright (c) 2013-2016 Avago Technologies - * All rights reserved. + * Copyright 2000-2020 Broadcom Inc. All rights reserved. * * * Name: mpi2.h @@ -44,7 +40,7 @@ * scatter/gather formats. * Creation Date: June 21, 2006 * - * mpi2.h Version: 02.00.48 + * mpi2.h Version: 02.00.52 * * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 * prefix are for use only on MPI v2.5 products, and must not be used @@ -153,6 +149,11 @@ * 09-02-16 02.00.46 Bumped MPI2_HEADER_VERSION_UNIT. * 11-23-16 02.00.47 Bumped MPI2_HEADER_VERSION_UNIT. * 02-03-17 02.00.48 Bumped MPI2_HEADER_VERSION_UNIT. + * 06-13-17 02.00.49 Bumped MPI2_HEADER_VERSION_UNIT. + * 09-29-17 02.00.50 Bumped MPI2_HEADER_VERSION_UNIT. + * 07-22-18 02.00.51 Added SECURE_BOOT define. + * Bumped MPI2_HEADER_VERSION_UNIT + * 08-15-18 02.00.52 Bumped MPI2_HEADER_VERSION_UNIT. * -------------------------------------------------------------------------- */ @@ -196,7 +197,7 @@ /* Unit and Dev versioning for this MPI header set */ -#define MPI2_HEADER_VERSION_UNIT (0x30) +#define MPI2_HEADER_VERSION_UNIT (0x34) #define MPI2_HEADER_VERSION_DEV (0x00) #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) @@ -297,6 +298,8 @@ typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS * Defines for the HostDiagnostic register */ #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) + +#define MPI26_DIAG_SECURE_BOOT (0x80000000) #define MPI2_DIAG_SBR_RELOAD (0x00002000) Modified: stable/12/sys/dev/mpr/mpi/mpi2_cnfg.h ============================================================================== --- stable/12/sys/dev/mpr/mpi/mpi2_cnfg.h Thu Sep 26 01:51:55 2019 (r352734) +++ stable/12/sys/dev/mpr/mpi/mpi2_cnfg.h Thu Sep 26 01:54:24 2019 (r352735) @@ -1,7 +1,5 @@ /*- - * Copyright (c) 2012-2015 LSI Corp. - * Copyright (c) 2013-2016 Avago Technologies - * All rights reserved. + * Copyright 2000-2020 Broadcom Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -27,22 +25,20 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD + * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD * * $FreeBSD$ */ /* - * Copyright (c) 2000-2015 LSI Corporation. - * Copyright (c) 2013-2016 Avago Technologies - * All rights reserved. + * Copyright 2000-2020 Broadcom Inc. All rights reserved. * * * Name: mpi2_cnfg.h * Title: MPI Configuration messages and pages * Creation Date: November 10, 2006 * - * mpi2_cnfg.h Version: 02.00.40 + * mpi2_cnfg.h Version: 02.00.45 * * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 * prefix are for use only on MPI v2.5 products, and must not be used @@ -259,6 +255,27 @@ * Added ChassisSlot field to SAS Enclosure Page 0. * Added ChassisSlot Valid bit (bit 5) to the Flags field * in SAS Enclosure Page 0. + * 06-13-17 02.00.41 Added MPI26_MFGPAGE_DEVID_SAS3816 and + * MPI26_MFGPAGE_DEVID_SAS3916 defines. + * Removed MPI26_MFGPAGE_DEVID_SAS4008 define. + * Added MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN define. + * Renamed PI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS to + * PI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN. + * Renamed MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS to + * MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK. + * 09-29-17 02.00.42 Added ControllerResetTO field to PCIe Device Page 2. + * Added NOIOB field to PCIe Device Page 2. + * Added MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN to + * the Capabilities field of PCIe Device Page 2. + * 07-22-18 02.00.43 Added defines for SAS3916 and SAS3816. + * Added WRiteCache defines to IO Unit Page 1. + * Added MaxEnclosureLevel to BIOS Page 1. + * Added OEMRD to SAS Enclosure Page 1. + * Added DMDReportPCIe to PCIe IO Unit Page 1. + * Added Flags field and flags for Retimers to + * PCIe Switch Page 1. + * 08-02-18 02.00.44 Added Slotx2, Slotx4 to ManPage 7. + * 08-15-18 02.00.45 Added ProductSpecific field at end of IOC Page 1 * -------------------------------------------------------------------------- */ @@ -601,9 +618,19 @@ typedef struct _MPI2_CONFIG_REPLY #define MPI26_MFGPAGE_DEVID_SAS3616 (0x00D1) #define MPI26_MFGPAGE_DEVID_SAS3708 (0x00D2) -#define MPI26_MFGPAGE_DEVID_SAS4008 (0x00A1) +#define MPI26_MFGPAGE_DEVID_SEC_MASK_SAS3916 (0x0003) +#define MPI26_MFGPAGE_DEVID_INVALID0_SAS3916 (0x00E0) +#define MPI26_MFGPAGE_DEVID_CFG_SEC_SAS3916 (0x00E1) +#define MPI26_MFGPAGE_DEVID_HARD_SEC_SAS3916 (0x00E2) +#define MPI26_MFGPAGE_DEVID_INVALID1_SAS3916 (0x00E3) +#define MPI26_MFGPAGE_DEVID_SEC_MASK_SAS3816 (0x0003) +#define MPI26_MFGPAGE_DEVID_INVALID0_SAS3816 (0x00E4) +#define MPI26_MFGPAGE_DEVID_CFG_SEC_SAS3816 (0x00E5) +#define MPI26_MFGPAGE_DEVID_HARD_SEC_SAS3816 (0x00E6) +#define MPI26_MFGPAGE_DEVID_INVALID1_SAS3816 (0x00E7) + /* Manufacturing Page 0 */ typedef struct _MPI2_CONFIG_PAGE_MAN_0 @@ -818,7 +845,8 @@ typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO U8 Location; /* 0x14 */ U8 ReceptacleID; /* 0x15 */ U16 Slot; /* 0x16 */ - U32 Reserved2; /* 0x18 */ + U16 Slotx4; /* 0x18 */ + U16 Slotx2; /* 0x1A */ } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO, Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t; @@ -960,6 +988,10 @@ typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) /* IO Unit Page 1 Flags defines */ +#define MPI26_IOUNITPAGE1_NVME_WRITE_CACHE_MASK (0x00030000) +#define MPI26_IOUNITPAGE1_NVME_WRITE_CACHE_ENABLE (0x00000000) +#define MPI26_IOUNITPAGE1_NVME_WRITE_CACHE_DISABLE (0x00010000) +#define MPI26_IOUNITPAGE1_NVME_WRITE_CACHE_NO_CHANGE (0x00020000) #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000) #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000) #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000) @@ -1384,7 +1416,7 @@ typedef struct _MPI2_CONFIG_PAGE_IOC_1 U8 PCIBusNum; /* 0x0E */ U8 PCIDomainSegment; /* 0x0F */ U32 Reserved1; /* 0x10 */ - U32 Reserved2; /* 0x14 */ + U32 ProductSpecific; /* 0x14 */ } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1, Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t; @@ -1510,7 +1542,7 @@ typedef struct _MPI2_CONFIG_PAGE_BIOS_1 U32 BiosOptions; /* 0x04 */ U32 IOCSettings; /* 0x08 */ U8 SSUTimeout; /* 0x0C */ - U8 Reserved1; /* 0x0D */ + U8 MaxEnclosureLevel; /* 0x0D */ U16 Reserved2; /* 0x0E */ U32 DeviceSettings; /* 0x10 */ U16 NumberOfDevices; /* 0x14 */ @@ -3102,7 +3134,9 @@ typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 U8 ChassisSlot; /* 0x1C */ U8 EnclosureLevel; /* 0x1D */ U16 SEPDevHandle; /* 0x1E */ - U32 Reserved2; /* 0x20 */ + U8 OEMRD; /* 0x20 */ + U8 Reserved1a; /* 0x21 */ + U16 Reserved2; /* 0x22 */ U32 Reserved3; /* 0x24 */ } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, @@ -3114,6 +3148,8 @@ typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x04) /* values for SAS Enclosure Page 0 Flags field */ +#define MPI26_SAS_ENCLS0_FLAGS_OEMRD_VALID (0x0080) +#define MPI26_SAS_ENCLS0_FLAGS_OEMRD_COLLECTING (0x0040) #define MPI2_SAS_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) @@ -3127,6 +3163,8 @@ typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 #define MPI26_ENCLOSURE0_PAGEVERSION (0x04) /* Values for Enclosure Page 0 Flags field */ +#define MPI26_ENCLS0_FLAGS_OEMRD_VALID (0x0080) +#define MPI26_ENCLS0_FLAGS_OEMRD_COLLECTING (0x0040) #define MPI26_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) #define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) #define MPI26_ENCLS0_FLAGS_MNG_MASK (0x000F) @@ -3502,8 +3540,9 @@ typedef struct _MPI26_PCIE_IO_UNIT1_PHY_DATA Mpi26PCIeIOUnit1PhyData_t, MPI2_POINTER pMpi26PCIeIOUnit1PhyData_t; /* values for LinkFlags */ -#define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS (0x00) -#define MPI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS (0x01) +#define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK (0x00) +#define MPI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN (0x01) +#define MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN (0x02) /* * Host code (drivers, BIOS, utilities, etc.) should leave this define set to @@ -3521,7 +3560,7 @@ typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_1 U16 AdditionalControlFlags; /* 0x0C */ U16 NVMeMaxQueueDepth; /* 0x0E */ U8 NumPhys; /* 0x10 */ - U8 Reserved1; /* 0x11 */ + U8 DMDReportPCIe; /* 0x11 */ U16 Reserved2; /* 0x12 */ MPI26_PCIE_IO_UNIT1_PHY_DATA PhyData[MPI26_PCIE_IOUNIT1_PHY_MAX];/* 0x14 */ } MPI26_CONFIG_PAGE_PIOUNIT_1, @@ -3542,6 +3581,13 @@ typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_1 #define MPI26_PCIEIOUNIT1_MAX_RATE_8_0 (0x40) #define MPI26_PCIEIOUNIT1_MAX_RATE_16_0 (0x50) +/* values for PCIe IO Unit Page 1 DMDReportPCIe */ +#define MPI26_PCIEIOUNIT1_DMD_REPORT_UNITS_MASK (0x80) +#define MPI26_PCIEIOUNIT1_DMD_REPORT_UNITS_1_SEC (0x00) +#define MPI26_PCIEIOUNIT1_DMD_REPORT_UNITS_16_SEC (0x80) +#define MPI26_PCIEIOUNIT1_DMD_REPORT_DELAY_TIME_MASK (0x7F) + + /* see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo values */ @@ -3585,16 +3631,22 @@ typedef struct _MPI26_CONFIG_PAGE_PSWITCH_1 U16 SwitchDevHandle; /* 0x10 */ U8 NegotiatedPortWidth; /* 0x12 */ U8 NegotiatedLinkRate; /* 0x13 */ - U32 Reserved4; /* 0x14 */ + U16 Flags; /* 0x14 */ + U16 Reserved4; /* 0x16 */ U32 Reserved5; /* 0x18 */ } MPI26_CONFIG_PAGE_PSWITCH_1, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PSWITCH_1, Mpi26PCIeSwitchPage1_t, MPI2_POINTER pMpi26PCIeSwitchPage1_t; -#define MPI26_PCIESWITCH1_PAGEVERSION (0x00) +#define MPI26_PCIESWITCH1_PAGEVERSION (0x00) /* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ +/* defines for the Flags field */ +#define MPI26_PCIESWITCH1_2_RETIMER_PRESENCE (0x0002) +#define MPI26_PCIESWITCH1_RETIMER_PRESENCE (0x0001) + + /**************************************************************************** * PCIe Device Config Pages (MPI v2.6 and later) ****************************************************************************/ @@ -3655,18 +3707,20 @@ typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_0 /* see mpi2_pci.h for the MPI26_PCIE_DEVINFO_ defines used for the DeviceInfo field */ /* values for PCIe Device Page 0 Flags field */ -#define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) -#define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH (0x4000) -#define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE (0x2000) -#define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION (0x0400) -#define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION (0x0200) -#define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE (0x0100) -#define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED (0x0080) -#define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED (0x0040) -#define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED (0x0020) -#define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED (0x0010) -#define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID (0x0002) -#define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT (0x0001) +#define MPI26_PCIEDEV0_FLAGS_2_RETIMER_PRESENCE (0x00020000) +#define MPI26_PCIEDEV0_FLAGS_RETIMER_PRESENCE (0x00010000) +#define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE (0x00008000) +#define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH (0x00004000) +#define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE (0x00002000) +#define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION (0x00000400) +#define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION (0x00000200) +#define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE (0x00000100) +#define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED (0x00000080) +#define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED (0x00000040) +#define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED (0x00000020) +#define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED (0x00000010) +#define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID (0x00000002) +#define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT (0x00000001) /* values for PCIe Device Page 0 SupportedLinkRates field */ #define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED (0x08) @@ -3683,19 +3737,25 @@ typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_2 { MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ U16 DevHandle; /* 0x08 */ - U16 Reserved1; /* 0x0A */ + U8 ControllerResetTO; /* 0x0A */ + U8 Reserved1; /* 0x0B */ U32 MaximumDataTransferSize;/* 0x0C */ U32 Capabilities; /* 0x10 */ - U32 Reserved2; /* 0x14 */ + U16 NOIOB; /* 0x14 */ + U16 Reserved2; /* 0x16 */ } MPI26_CONFIG_PAGE_PCIEDEV_2, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIEDEV_2, Mpi26PCIeDevicePage2_t, MPI2_POINTER pMpi26PCIeDevicePage2_t; -#define MPI26_PCIEDEVICE2_PAGEVERSION (0x00) +#define MPI26_PCIEDEVICE2_PAGEVERSION (0x01) /* defines for PCIe Device Page 2 Capabilities field */ -#define MPI26_PCIEDEV2_CAP_SGL_FORMAT (0x00000004) -#define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT (0x00000002) -#define MPI26_PCIEDEV2_CAP_SGL_SUPPORT (0x00000001) +#define MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN (0x00000008) +#define MPI26_PCIEDEV2_CAP_SGL_FORMAT (0x00000004) +#define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT (0x00000002) +#define MPI26_PCIEDEV2_CAP_SGL_SUPPORT (0x00000001) + +/* Defines for the NOIOB field */ +#define MPI26_PCIEDEV2_NOIOB_UNSUPPORTED (0x0000) /**************************************************************************** Modified: stable/12/sys/dev/mpr/mpi/mpi2_hbd.h ============================================================================== --- stable/12/sys/dev/mpr/mpi/mpi2_hbd.h Thu Sep 26 01:51:55 2019 (r352734) +++ stable/12/sys/dev/mpr/mpi/mpi2_hbd.h Thu Sep 26 01:54:24 2019 (r352735) @@ -1,7 +1,5 @@ /*- - * Copyright (c) 2012-2015 LSI Corp. - * Copyright (c) 2013-2016 Avago Technologies - * All rights reserved. + * Copyright 2000-2020 Broadcom Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -27,15 +25,13 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD + * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD * * $FreeBSD$ */ /* - * Copyright (c) 2009-2015 LSI Corporation. - * Copyright (c) 2013-2016 Avago Technologies - * All rights reserved. + * Copyright 2000-2020 Broadcom Inc. All rights reserved. * * * Name: mpi2_hbd.h Modified: stable/12/sys/dev/mpr/mpi/mpi2_history.txt ============================================================================== --- stable/12/sys/dev/mpr/mpi/mpi2_history.txt Thu Sep 26 01:51:55 2019 (r352734) +++ stable/12/sys/dev/mpr/mpi/mpi2_history.txt Thu Sep 26 01:54:24 2019 (r352735) @@ -1,7 +1,5 @@ /*- - * Copyright (c) 2012-2015 LSI Corp. - * Copyright (c) 2013-2016 Avago Technologies - * All rights reserved. + * Copyright 2000-2020 Broadcom Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -27,7 +25,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD + * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD * * $FreeBSD$ */ @@ -36,21 +34,19 @@ Fusion-MPT MPI 2.0 / 2.5 Header File Change History ============================== - Copyright (c) 2000-2015 LSI Corporation. - Copyright (c) 2013-2016 Avago Technologies - All rights reserved. + Copyright 2000-2020 Broadcom Inc. All rights reserved. --------------------------------------- - Header Set Release Version: 02.00.48 - Header Set Release Date: 02-03-17 + Header Set Release Version: 02.00.50 + Header Set Release Date: 09-29-17 --------------------------------------- Filename Current version Prior version ---------- --------------- ------------- - mpi2.h 02.00.48 02.00.47 - mpi2_cnfg.h 02.00.40 02.00.39 + mpi2.h 02.00.50 02.00.49 + mpi2_cnfg.h 02.00.42 02.00.41 mpi2_init.h 02.00.21 02.00.21 - mpi2_ioc.h 02.00.32 02.00.31 + mpi2_ioc.h 02.00.34 02.00.33 mpi2_raid.h 02.00.11 02.00.11 mpi2_sas.h 02.00.10 02.00.10 mpi2_targ.h 02.00.09 02.00.09 @@ -59,7 +55,7 @@ mpi2_ra.h 02.00.01 02.00.01 mpi2_hbd.h 02.00.04 02.00.04 mpi2_pci.h 02.00.02 02.00.02 - mpi2_history.txt 02.00.45 02.00.44 + mpi2_history.txt 02.00.46 02.00.45 * Date Version Description @@ -163,6 +159,8 @@ mpi2.h * 09-02-16 02.00.46 Bumped MPI2_HEADER_VERSION_UNIT. * 11-23-16 02.00.47 Bumped MPI2_HEADER_VERSION_UNIT. * 02-03-17 02.00.48 Bumped MPI2_HEADER_VERSION_UNIT. + * 06-13-17 02.00.49 Bumped MPI2_HEADER_VERSION_UNIT. + * 09-29-17 02.00.50 Bumped MPI2_HEADER_VERSION_UNIT. * -------------------------------------------------------------------------- mpi2_cnfg.h @@ -371,6 +369,18 @@ mpi2_cnfg.h * Added ChassisSlot field to SAS Enclosure Page 0. * Added ChassisSlot Valid bit (bit 5) to the Flags field * in SAS Enclosure Page 0. + * 06-13-17 02.00.41 Added MPI26_MFGPAGE_DEVID_SAS3816 and + * MPI26_MFGPAGE_DEVID_SAS3916 defines. + * Removed MPI26_MFGPAGE_DEVID_SAS4008 define. + * Added MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN define. + * Renamed MPI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS to + * MPI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN. + * Renamed MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS to + * MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK. + * 09-29-17 02.00.42 Added ControllerResetTO field to PCIe Device Page 2. + * Added NOIOB field to PCIe Device Page 2. + * Added MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN to + * the Capabilities field of PCIe Device Page 2. * -------------------------------------------------------------------------- mpi2_init.h @@ -566,6 +576,10 @@ mpi2_ioc.h * 02-02-17 02.00.32 Added MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP. * Added MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT and related * defines for the ReasonCode field. + * 06-13-17 02.00.33 Added MPI2_FW_DOWNLOAD_ITYPE_CPLD. + * 09-29-17 02.00.34 Added MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED + * to the ReasonCode field in PCIe Device Status Change + * Event Data. * -------------------------------------------------------------------------- mpi2_raid.h @@ -687,20 +701,20 @@ mpi2_pci.h mpi2_history.txt Parts list history -Filename 02.00.48 ----------- -------- -mpi2.h 02.00.48 -mpi2_cnfg.h 02.00.40 -mpi2_init.h 02.00.21 -mpi2_ioc.h 02.00.32 -mpi2_raid.h 02.00.11 -mpi2_sas.h 02.00.10 -mpi2_targ.h 02.00.09 -mpi2_tool.h 02.00.14 -mpi2_type.h 02.00.01 -mpi2_ra.h 02.00.01 -mpi2_hbd.h 02.00.04 -mpi2_pci.h 02.00.02 +Filename 02.00.50 02.00.49 02.00.48 +---------- -------- -------- -------- +mpi2.h 02.00.50 02.00.49 02.00.48 +mpi2_cnfg.h 02.00.42 02.00.41 02.00.40 +mpi2_init.h 02.00.21 02.00.21 02.00.21 +mpi2_ioc.h 02.00.34 02.00.33 02.00.32 +mpi2_raid.h 02.00.11 02.00.11 02.00.11 +mpi2_sas.h 02.00.10 02.00.10 02.00.10 +mpi2_targ.h 02.00.09 02.00.09 02.00.09 +mpi2_tool.h 02.00.14 02.00.14 02.00.14 +mpi2_type.h 02.00.01 02.00.01 02.00.01 +mpi2_ra.h 02.00.01 02.00.01 02.00.01 +mpi2_hbd.h 02.00.04 02.00.04 02.00.04 +mpi2_pci.h 02.00.02 02.00.02 02.00.02 Filename 02.00.47 02.00.46 02.00.45 02.00.44 02.00.43 02.00.42 ---------- -------- -------- -------- -------- -------- -------- Modified: stable/12/sys/dev/mpr/mpi/mpi2_init.h ============================================================================== --- stable/12/sys/dev/mpr/mpi/mpi2_init.h Thu Sep 26 01:51:55 2019 (r352734) +++ stable/12/sys/dev/mpr/mpi/mpi2_init.h Thu Sep 26 01:54:24 2019 (r352735) @@ -1,7 +1,5 @@ /*- - * Copyright (c) 2012-2015 LSI Corp. - * Copyright (c) 2013-2016 Avago Technologies - * All rights reserved. + * Copyright 2000-2020 Broadcom Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -27,15 +25,13 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD + * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD * * $FreeBSD$ */ /* - * Copyright (c) 2000-2015 LSI Corporation. - * Copyright (c) 2013-2016 Avago Technologies - * All rights reserved. + * Copyright 2000-2020 Broadcom Inc. All rights reserved. * * * Name: mpi2_init.h @@ -62,7 +58,7 @@ * 05-21-08 02.00.05 Fixed typo in name of Mpi2SepRequest_t. * 10-02-08 02.00.06 Removed Untagged and No Disconnect values from SCSI IO * Control field Task Attribute flags. - * Moved LUN field defines to mpi2.h because they are + * Moved LUN field defines to mpi2.h becasue they are * common to many structures. * 05-06-09 02.00.07 Changed task management type of Query Unit Attention to * Query Asynchronous Event. Modified: stable/12/sys/dev/mpr/mpi/mpi2_ioc.h ============================================================================== --- stable/12/sys/dev/mpr/mpi/mpi2_ioc.h Thu Sep 26 01:51:55 2019 (r352734) +++ stable/12/sys/dev/mpr/mpi/mpi2_ioc.h Thu Sep 26 01:54:24 2019 (r352735) @@ -1,7 +1,5 @@ /*- - * Copyright (c) 2012-2015 LSI Corp. - * Copyright (c) 2013-2016 Avago Technologies - * All rights reserved. + * Copyright 2000-2020 Broadcom Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -27,22 +25,20 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD + * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD * * $FreeBSD$ */ /* - * Copyright (c) 2000-2015 LSI Corporation. - * Copyright (c) 2013-2016 Avago Technologies - * All rights reserved. + * Copyright 2000-2020 Broadcom Inc. All rights reserved. * * * Name: mpi2_ioc.h * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages * Creation Date: October 11, 2006 * - * mpi2_ioc.h Version: 02.00.32 + * mpi2_ioc.h Version: 02.00.36 * * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 * prefix are for use only on MPI v2.5 products, and must not be used @@ -205,6 +201,13 @@ * 02-02-17 02.00.32 Added MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP. * Added MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT and related * defines for the ReasonCode field. + * 06-13-17 02.00.33 Added MPI2_FW_DOWNLOAD_ITYPE_CPLD. + * 09-29-17 02.00.34 Added MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED + * to the ReasonCode field in PCIe Device Status Change + * Event Data. + * 07-22-18 02.00.35 Added FW_DOWNLOAD_ITYPE_CPLD and _PSOC. + * Moved FW image definitions ionto new mpi2_image,h + * 08-14-18 02.00.36 Fixed definition of MPI2_FW_DOWNLOAD_ITYPE_PSOC (0x16) * -------------------------------------------------------------------------- */ @@ -1270,6 +1273,7 @@ typedef struct _MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CH #define MPI26_EVENT_PCIDEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) #define MPI26_EVENT_PCIDEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) #define MPI26_EVENT_PCIDEV_STAT_RC_DEV_INIT_FAILURE (0x10) +#define MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED (0x11) /* PCIe Enumeration Event data (MPI v2.6 and later) */ @@ -1534,8 +1538,12 @@ typedef struct _MPI2_FW_DOWNLOAD_REQUEST #define MPI2_FW_DOWNLOAD_ITYPE_CTLR (0x12) #define MPI2_FW_DOWNLOAD_ITYPE_IMR_FIRMWARE (0x13) #define MPI2_FW_DOWNLOAD_ITYPE_MR_NVDATA (0x14) +#define MPI2_FW_DOWNLOAD_ITYPE_CPLD (0x15) /* MPI v2.6 and newer */ +#define MPI2_FW_DOWNLOAD_ITYPE_PSOC (0x16) /* MPI v2.6 and newer */ #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0) +#define MPI2_FW_DOWNLOAD_ITYPE_TERMINATE (0xFF) /* MPI v2.6 and newer */ + /* MPI v2.0 FWDownload TransactionContext Element */ typedef struct _MPI2_FW_DOWNLOAD_TCSGE { @@ -1692,367 +1700,6 @@ typedef struct _MPI2_FW_UPLOAD_REPLY } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY, Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t; - -/* FW Image Header */ -typedef struct _MPI2_FW_IMAGE_HEADER -{ - U32 Signature; /* 0x00 */ - U32 Signature0; /* 0x04 */ - U32 Signature1; /* 0x08 */ - U32 Signature2; /* 0x0C */ - MPI2_VERSION_UNION MPIVersion; /* 0x10 */ - MPI2_VERSION_UNION FWVersion; /* 0x14 */ - MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */ - MPI2_VERSION_UNION PackageVersion; /* 0x1C */ - U16 VendorID; /* 0x20 */ - U16 ProductID; /* 0x22 */ - U16 ProtocolFlags; /* 0x24 */ - U16 Reserved26; /* 0x26 */ - U32 IOCCapabilities; /* 0x28 */ - U32 ImageSize; /* 0x2C */ - U32 NextImageHeaderOffset; /* 0x30 */ - U32 Checksum; /* 0x34 */ - U32 Reserved38; /* 0x38 */ - U32 Reserved3C; /* 0x3C */ - U32 Reserved40; /* 0x40 */ - U32 Reserved44; /* 0x44 */ - U32 Reserved48; /* 0x48 */ - U32 Reserved4C; /* 0x4C */ - U32 Reserved50; /* 0x50 */ - U32 Reserved54; /* 0x54 */ - U32 Reserved58; /* 0x58 */ - U32 Reserved5C; /* 0x5C */ - U32 BootFlags; /* 0x60 */ /* reserved in MPI v2.5 and earlier */ - U32 FirmwareVersionNameWhat; /* 0x64 */ - U8 FirmwareVersionName[32]; /* 0x68 */ - U32 VendorNameWhat; /* 0x88 */ - U8 VendorName[32]; /* 0x8C */ - U32 PackageNameWhat; /* 0x88 */ - U8 PackageName[32]; /* 0x8C */ - U32 ReservedD0; /* 0xD0 */ - U32 ReservedD4; /* 0xD4 */ - U32 ReservedD8; /* 0xD8 */ - U32 ReservedDC; /* 0xDC */ - U32 ReservedE0; /* 0xE0 */ - U32 ReservedE4; /* 0xE4 */ - U32 ReservedE8; /* 0xE8 */ - U32 ReservedEC; /* 0xEC */ - U32 ReservedF0; /* 0xF0 */ - U32 ReservedF4; /* 0xF4 */ - U32 ReservedF8; /* 0xF8 */ - U32 ReservedFC; /* 0xFC */ -} MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER, - Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t; - -/* Signature field */ -#define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00) -#define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000) -#define MPI2_FW_HEADER_SIGNATURE (0xEA000000) -#define MPI26_FW_HEADER_SIGNATURE (0xEB000000) - -/* Signature0 field */ -#define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04) -#define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A) -#define MPI26_FW_HEADER_SIGNATURE0_BASE (0x5AEAA500) /* Last byte is defined by architecture */ -#define MPI26_FW_HEADER_SIGNATURE0_ARC_0 (0x5A) -#define MPI26_FW_HEADER_SIGNATURE0_ARC_1 (0x00) -#define MPI26_FW_HEADER_SIGNATURE0_ARC_2 (0x01) -#define MPI26_FW_HEADER_SIGNATURE0_ARC_3 (0x02) -#define MPI26_FW_HEADER_SIGNATURE0 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_0) // legacy (0x5AEAA55A) -#define MPI26_FW_HEADER_SIGNATURE0_3516 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_1) -#define MPI26_FW_HEADER_SIGNATURE0_4008 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_3) - -/* Signature1 field */ -#define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08) -#define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5) -#define MPI26_FW_HEADER_SIGNATURE1 (0xA55AEAA5) - -/* Signature2 field */ -#define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C) -#define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA) -#define MPI26_FW_HEADER_SIGNATURE2 (0x5AA55AEA) - - -/* defines for using the ProductID field */ -#define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000) -#define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000) - -#define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00) -#define MPI2_FW_HEADER_PID_PROD_A (0x0000) -#define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200) -#define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700) - - -#define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF) -/* SAS ProductID Family bits */ -#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013) -#define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014) -#define MPI25_FW_HEADER_PID_FAMILY_3108_SAS (0x0021) -#define MPI26_FW_HEADER_PID_FAMILY_3324_SAS (0x0028) -#define MPI26_FW_HEADER_PID_FAMILY_3516_SAS (0x0031) - -/* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */ - -/* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */ - - -#define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C) -#define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30) -#define MPI26_FW_HEADER_BOOTFLAGS_OFFSET (0x60) -#define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64) - -#define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840) - -#define MPI2_FW_HEADER_SIZE (0x100) - - -/* Extended Image Header */ -typedef struct _MPI2_EXT_IMAGE_HEADER - -{ - U8 ImageType; /* 0x00 */ - U8 Reserved1; /* 0x01 */ - U16 Reserved2; /* 0x02 */ - U32 Checksum; /* 0x04 */ - U32 ImageSize; /* 0x08 */ - U32 NextImageHeaderOffset; /* 0x0C */ - U32 PackageVersion; /* 0x10 */ - U32 Reserved3; /* 0x14 */ - U32 Reserved4; /* 0x18 */ - U32 Reserved5; /* 0x1C */ - U8 IdentifyString[32]; /* 0x20 */ -} MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER, - Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t; - -/* useful offsets */ -#define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00) -#define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08) -#define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C) - -#define MPI2_EXT_IMAGE_HEADER_SIZE (0x40) - -/* defines for the ImageType field */ -#define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) -#define MPI2_EXT_IMAGE_TYPE_FW (0x01) -#define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03) -#define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04) -#define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05) -#define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06) -#define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07) -#define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08) -#define MPI2_EXT_IMAGE_TYPE_ENCRYPTED_HASH (0x09) /* MPI v2.5 and newer */ -#define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80) -#define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xFF) - -#define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC) /* deprecated */ - - - -/* FLASH Layout Extended Image Data */ - -/* - * Host code (drivers, BIOS, utilities, etc.) should leave this define set to - * one and check RegionsPerLayout at runtime. - */ -#ifndef MPI2_FLASH_NUMBER_OF_REGIONS -#define MPI2_FLASH_NUMBER_OF_REGIONS (1) -#endif - -/* - * Host code (drivers, BIOS, utilities, etc.) should leave this define set to - * one and check NumberOfLayouts at runtime. - */ -#ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS -#define MPI2_FLASH_NUMBER_OF_LAYOUTS (1) -#endif - -typedef struct _MPI2_FLASH_REGION -{ - U8 RegionType; /* 0x00 */ - U8 Reserved1; /* 0x01 */ - U16 Reserved2; /* 0x02 */ - U32 RegionOffset; /* 0x04 */ - U32 RegionSize; /* 0x08 */ - U32 Reserved3; /* 0x0C */ -} MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION, - Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t; - -typedef struct _MPI2_FLASH_LAYOUT -{ - U32 FlashSize; /* 0x00 */ - U32 Reserved1; /* 0x04 */ - U32 Reserved2; /* 0x08 */ - U32 Reserved3; /* 0x0C */ - MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */ -} MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT, - Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t; - -typedef struct _MPI2_FLASH_LAYOUT_DATA -{ - U8 ImageRevision; /* 0x00 */ - U8 Reserved1; /* 0x01 */ - U8 SizeOfRegion; /* 0x02 */ - U8 Reserved2; /* 0x03 */ - U16 NumberOfLayouts; /* 0x04 */ - U16 RegionsPerLayout; /* 0x06 */ - U16 MinimumSectorAlignment; /* 0x08 */ - U16 Reserved3; /* 0x0A */ - U32 Reserved4; /* 0x0C */ - MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */ -} MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA, - Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t; - -/* defines for the RegionType field */ -#define MPI2_FLASH_REGION_UNUSED (0x00) -#define MPI2_FLASH_REGION_FIRMWARE (0x01) -#define MPI2_FLASH_REGION_BIOS (0x02) -#define MPI2_FLASH_REGION_NVDATA (0x03) -#define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05) -#define MPI2_FLASH_REGION_MFG_INFORMATION (0x06) -#define MPI2_FLASH_REGION_CONFIG_1 (0x07) -#define MPI2_FLASH_REGION_CONFIG_2 (0x08) -#define MPI2_FLASH_REGION_MEGARAID (0x09) -#define MPI2_FLASH_REGION_COMMON_BOOT_BLOCK (0x0A) -#define MPI2_FLASH_REGION_INIT (MPI2_FLASH_REGION_COMMON_BOOT_BLOCK) /* older name */ -#define MPI2_FLASH_REGION_CBB_BACKUP (0x0D) -#define MPI2_FLASH_REGION_SBR (0x0E) -#define MPI2_FLASH_REGION_SBR_BACKUP (0x0F) -#define MPI2_FLASH_REGION_HIIM (0x10) -#define MPI2_FLASH_REGION_HIIA (0x11) -#define MPI2_FLASH_REGION_CTLR (0x12) -#define MPI2_FLASH_REGION_IMR_FIRMWARE (0x13) -#define MPI2_FLASH_REGION_MR_NVDATA (0x14) - -/* ImageRevision */ -#define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00) - - - -/* Supported Devices Extended Image Data */ - -/* - * Host code (drivers, BIOS, utilities, etc.) should leave this define set to - * one and check NumberOfDevices at runtime. - */ -#ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES -#define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1) -#endif - -typedef struct _MPI2_SUPPORTED_DEVICE -{ - U16 DeviceID; /* 0x00 */ - U16 VendorID; /* 0x02 */ - U16 DeviceIDMask; /* 0x04 */ - U16 Reserved1; /* 0x06 */ - U8 LowPCIRev; /* 0x08 */ - U8 HighPCIRev; /* 0x09 */ - U16 Reserved2; /* 0x0A */ - U32 Reserved3; /* 0x0C */ -} MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE, - Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t; - -typedef struct _MPI2_SUPPORTED_DEVICES_DATA -{ - U8 ImageRevision; /* 0x00 */ - U8 Reserved1; /* 0x01 */ - U8 NumberOfDevices; /* 0x02 */ - U8 Reserved2; /* 0x03 */ - U32 Reserved3; /* 0x04 */ - MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */ -} MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA, - Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t; - -/* ImageRevision */ -#define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00) - - -/* Init Extended Image Data */ - -typedef struct _MPI2_INIT_IMAGE_FOOTER - -{ - U32 BootFlags; /* 0x00 */ - U32 ImageSize; /* 0x04 */ - U32 Signature0; /* 0x08 */ - U32 Signature1; /* 0x0C */ - U32 Signature2; /* 0x10 */ - U32 ResetVector; /* 0x14 */ -} MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER, - Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t; - -/* defines for the BootFlags field */ -#define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00) - -/* defines for the ImageSize field */ -#define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04) - -/* defines for the Signature0 field */ -#define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08) -#define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA) - -/* defines for the Signature1 field */ -#define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C) -#define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5) - -/* defines for the Signature2 field */ -#define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10) -#define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A) - -/* Signature fields as individual bytes */ -#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA) -#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A) -#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5) -#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A) - -#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5) -#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA) -#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A) -#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5) - -#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A) -#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5) -#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA) -#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A) - -/* defines for the ResetVector field */ -#define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14) - - -/* Encrypted Hash Extended Image Data */ - -typedef struct _MPI25_ENCRYPTED_HASH_ENTRY -{ - U8 HashImageType; /* 0x00 */ - U8 HashAlgorithm; /* 0x01 */ - U8 EncryptionAlgorithm; /* 0x02 */ - U8 Reserved1; /* 0x03 */ - U32 Reserved2; /* 0x04 */ - U32 EncryptedHash[1]; /* 0x08 */ /* variable length */ -} MPI25_ENCRYPTED_HASH_ENTRY, MPI2_POINTER PTR_MPI25_ENCRYPTED_HASH_ENTRY, - Mpi25EncryptedHashEntry_t, MPI2_POINTER pMpi25EncryptedHashEntry_t; - -/* values for HashImageType */ -#define MPI25_HASH_IMAGE_TYPE_UNUSED (0x00) -#define MPI25_HASH_IMAGE_TYPE_FIRMWARE (0x01) -#define MPI25_HASH_IMAGE_TYPE_BIOS (0x02) - -/* values for HashAlgorithm */ -#define MPI25_HASH_ALGORITHM_UNUSED (0x00) -#define MPI25_HASH_ALGORITHM_SHA256 (0x01) - -/* values for EncryptionAlgorithm */ -#define MPI25_ENCRYPTION_ALG_UNUSED (0x00) -#define MPI25_ENCRYPTION_ALG_RSA256 (0x01) - -typedef struct _MPI25_ENCRYPTED_HASH_DATA -{ - U8 ImageVersion; /* 0x00 */ - U8 NumHash; /* 0x01 */ - U16 Reserved1; /* 0x02 */ - U32 Reserved2; /* 0x04 */ - MPI25_ENCRYPTED_HASH_ENTRY EncryptedHashEntry[1]; /* 0x08 */ /* variable number of entries */ -} MPI25_ENCRYPTED_HASH_DATA, MPI2_POINTER PTR_MPI25_ENCRYPTED_HASH_DATA, - Mpi25EncryptedHashData_t, MPI2_POINTER pMpi25EncryptedHashData_t; /**************************************************************************** * PowerManagementControl message Modified: stable/12/sys/dev/mpr/mpi/mpi2_pci.h ============================================================================== --- stable/12/sys/dev/mpr/mpi/mpi2_pci.h Thu Sep 26 01:51:55 2019 (r352734) +++ stable/12/sys/dev/mpr/mpi/mpi2_pci.h Thu Sep 26 01:54:24 2019 (r352735) @@ -1,7 +1,5 @@ /*- - * Copyright (c) 2012-2015 LSI Corp. - * Copyright (c) 2013-2016 Avago Technologies - * All rights reserved. + * Copyright 2000-2020 Broadcom Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -27,22 +25,20 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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