Date: Thu, 13 Oct 2011 08:26:28 +0000 (UTC) From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-user@freebsd.org Subject: svn commit: r226334 - user/adrian/if_ath_tx/sys/dev/hwpmc Message-ID: <201110130826.p9D8QSrJ006558@svn.freebsd.org>
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Author: adrian Date: Thu Oct 13 08:26:28 2011 New Revision: 226334 URL: http://svn.freebsd.org/changeset/base/226334 Log: * Add interrupt bit for sampling * Fix sampling set/read macro to correctly work for mips24k sampling. The interrupt is asserted when bit 31 = 1, not when the counter overflows. Modified: user/adrian/if_ath_tx/sys/dev/hwpmc/hwpmc_mips24k.h Modified: user/adrian/if_ath_tx/sys/dev/hwpmc/hwpmc_mips24k.h ============================================================================== --- user/adrian/if_ath_tx/sys/dev/hwpmc/hwpmc_mips24k.h Thu Oct 13 08:26:23 2011 (r226333) +++ user/adrian/if_ath_tx/sys/dev/hwpmc/hwpmc_mips24k.h Thu Oct 13 08:26:28 2011 (r226334) @@ -39,13 +39,24 @@ #define MIPS24K_PMC_USER_ENABLE 0x08 /* Count in USER mode */ #define MIPS24K_PMC_SUPER_ENABLE 0x04 /* Count in SUPERVISOR mode */ #define MIPS24K_PMC_KERNEL_ENABLE 0x02 /* Count in KERNEL mode */ +#define MIPS24K_PMC_INTERRUPT_ENABLE 0x10 /* + * Signal interrupt when + * bit 31 of the counter is set + */ #define MIPS24K_PMC_ENABLE (MIPS24K_PMC_USER_ENABLE | \ MIPS24K_PMC_SUPER_ENABLE | \ MIPS24K_PMC_KERNEL_ENABLE) -#define MIPS24K_RELOAD_COUNT_TO_PERFCTR_VALUE(R) (-(R)) -#define MIPS24K_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (-(P)) +/* + * The mips24k performance counters wire bit 31 to the PC interrupt + * (and likely the PC cause bit when causing a trap.) + * + * Thus the correct value to initialise the counter is 0x7fffffff - + * sample value. + */ +#define MIPS24K_RELOAD_COUNT_TO_PERFCTR_VALUE(R) (0x7fffffff-(R)) +#define MIPS24K_PERFCTR_VALUE_TO_RELOAD_COUNT(P) ((P) - 0x7fffffff) #define MIPS24K_PMC_SELECT 0x4 /* Which bit position the event starts at. */ #define MIPS24K_PMC_OFFSET 2 /* Control registers are 0, 2, 4, etc. */
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